CXD2598 Ver la hoja de datos (PDF) - Sony Semiconductor
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CXD2598 Datasheet PDF : 147 Pages
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CXD2598Q
Contents
§1. CPU Interface
§1-1. CPU Interface Timing ..........................................................................................................................15
§1-2. CPU Interface Command Table ..........................................................................................................15
§1-3. CPU Command Presets ......................................................................................................................26
§1-4. Description of SENS Signals ...............................................................................................................32
§1-5. Description of Commands ...................................................................................................................34
§2. Subcode Interface
§2-1. P to W Subcode Readout ....................................................................................................................62
§2-2. 80-bit Sub-Q Readout..........................................................................................................................62
§3. Description of Modes
§3-1. CLV-N Mode ........................................................................................................................................69
§3-2. CLV-W Mode .......................................................................................................................................69
§3-3. CAV-W Mode.......................................................................................................................................69
§3-4. VCO-C mode .......................................................................................................................................70
§4. Description of Other Functions
§4-1. Channel Clock Recovery by Digital PLL Circuit...................................................................................73
§4-2. Frame Sync Protection ........................................................................................................................75
§4-3. Error Correction ...................................................................................................................................75
§4-4. DA Interface.........................................................................................................................................76
§4-5. Digital Out ............................................................................................................................................78
§4-6. Servo Auto Sequence..........................................................................................................................82
§4-7. Digital CLV...........................................................................................................................................90
§4-8. CD-DSP Block Playback Speed ..........................................................................................................91
§4-9. DAC Block Playback Speed ................................................................................................................91
§4-10. DAC Block Input Timing ....................................................................................................................92
§4-11. Description of DAC Block Functions..................................................................................................92
§4-12. LPF Block ..........................................................................................................................................97
§4-13. Asymmetry Correction .......................................................................................................................98
§4-14. CD TEXT Data Demodulation ...........................................................................................................99
§5. Description of Servo Signal Processing System Functions and Commands
§5-1. General Description of Servo Signal Processing System..................................................................101
§5-2. Digital Servo Block Master Clock (MCK) ...........................................................................................102
§5-3. DC Offset Cancel [AVRG Measurement and Compensation] ...........................................................103
§5-4. E:F Balance Adjustment Function .....................................................................................................104
§5-5. FCS Bias Adjustment Function..........................................................................................................104
§5-6. AGCNTL Function .............................................................................................................................106
§5-7. FCS Servo and FCS Search .............................................................................................................108
§5-8. TRK and SLD Servo Control .............................................................................................................109
§5-9. MIRR and DFCT Signal Generation ..................................................................................................110
§5-10. DFCT Countermeasure Circuit ........................................................................................................111
§5-11. Anti-Shock Circuit ............................................................................................................................111
§5-12. Brake Circuit ....................................................................................................................................112
§5-13. COUT Signal ...................................................................................................................................113
§5-14. Serial Readout Circuit......................................................................................................................113
§5-15. Writing to Coefficient RAM ..............................................................................................................114
§5-16. PWM Output ....................................................................................................................................114
§5-17. Servo Status Changes Produced by LOCK Signal ........................................................................115
§5-18. Description of Commands and Data Sets .......................................................................................115
§5-19. List of Servo Filter Coefficients ........................................................................................................137
§5-20. Filter Composition............................................................................................................................139
§5-21. TRACKING and FOCUS Frequency Response ..............................................................................145
§6. Application Circuit ...................................................................................................................................146
Explanation of abbreviations
AVRG: Average
AGCNTL: Auto gain control
FCS:
Focus
– 14 –
TRK:
SLD:
DFCT:
Tracking
Sled
Defect
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