CXD1261 Ver la hoja de datos (PDF) - Sony Semiconductor

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CXD1261

Sync Signal, Timing Signal Generator for CCD Cameras

Sony Semiconductor 

CXD1261AR

External Reset Description

H Reset (HR)

The reset is performed at the first falling edge of the reset pulse that was input; resets are not performed at

subsequent edges as long as they do not deviate by two clock pulses (0.14µs) or more.

The minimum reset pulse width is 0.35µs. In addition, HD immediately after a reset can not be guaranteed.

The position at which the reset is performed is 2.31µs advanced after the H reset input.

H reset input

HD output

0.35µs or more

2.31µs

V Reset (VR)

The falling edge of V reset pulse that was input is field identified by the phase difference with the internal signal

(field judge pulse) defined by the falling edge of HD. And VD is reset in phase with V reset pulse.

When field judge pulse is low and V reset pulse falls,

EIA: VD falling edge after 262.5H is the relation between HD and VD of EVEN field.

CCIR: VD falling edge after 313.5H is the relation between HD and VD of ODD field.

Also, when field judge pulse is high and V reset pulse falls,

EIA: VD falling edge after 262.5H is the relation between HD and VD of ODD field.

CCIR: VD falling edge after 313.5H is the relation between HD and VD of EVEN field.

The minimum reset pulse width is 64µs.

1

2

HD output

262

263

264

The value without ( ) is for EIA

3

(312) (313)

(314)

The value in ( ) is for CCIR

Field

judge

pulse

VR input

VD output

(EIA)

VD output

(CCIR)

64µs or more

VD timing is genarated after

262.5H with this VR timing

1HD

VD timing is genarated after

313.5H with this VR timing

Note: For CCIR, VD output is delayed 1HD in relation to VR input.

–7–

1HD

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