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CX5000

0.18um Structured ASIC

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CX5000:

0.18um Structured ASIC Product Family

The CX5000 family has a flexible I/O structure. Each metal-programmable I/O driver cell supports one or

two pads, depending on the I/O configuration chosen. The CX5000 product line can be packaged in

conventional IC packaging, provided as bare die or processed with an extra layer of metal, bumped and

then mounted into a flip-chip package. ChipX has a vast library of standard packages, large pin count

FPGA packages, military and hermetic packages. Custom package development services are reasonably

priced and include multi-chip modules as well as exotic, ultra-fine pitch and very small outline package

types.

CX5000 Architecture: Core, Memory, Corner, I/O Ring

Core

The CX5000 core logic is divided into logic modules each with a closely packed, optimized transistor

layout separated by routing channels. The placer software configures the logic modules using pre-defined

templates in the top two metal layers to perform the 400 or so library elements supported by the CX5000

technology. Via stacks are used to bring module internal signals up to the programming layers, where

they are connected to form the logic function.

The library of logic components described in the CX5000 Data Book uses variously one, two, and

sometimes three logic modules. The Synthesis Engine is instructed to use the most complex

combinatorial logic components possible to ensure best utilization of each logic module. The router is

used to wire up the global routing resources and make short distance connections between the logic

modules in the routing channels. The routing channels contain lengthwise and crosswise metal wires of

various fetches connected to each other and to the logic modules using the top two metal layers.

The CX5000 core logic operates at clock speeds in excess of 200MHz. The applications targeted for

standard cell generally operate at 90% of the standard cell performance and considerably faster than

FPGAs. A two input NAND gate in CX5000 technology typically contributes just 180ps of delay to a logic

path.

The CX5000 is optimized for low power

consumption. Table 2 outlines the power budget

of the CX5000 core components.

TABLE 2.

CX5000 CORE COMPONENTS POWER BUDGET

Flip Flop Constant Data (uW/MHz) Typical

0.076

Flip Flop Toggling Data (uW/MHz) Typical

0.49

Memory

Logic Cell (uW/MHz) Typical

0.25

The CX5000 has two memory types. Flexible CX-Memory blocks are arranged at the bottom of the

masterslice and extend across the entire width of the chip. Each memory represents 16K bits of available

2ns block SRAM or ROM with two address decoders, two input ports, and two output ports. As shown in

Figure 1 (next page), the address decoders can be used to address two separate 8K bit memory

instances or one 8K bit dual-port memory instance. Each memory may be as narrow as 2 bits or as wide

as 64 bits, with corresponding depth.

In addition, each CX5000 masterslice contains multiple blocks of 18Kbit fast dual port SRAM arranged as

36bits x 512 locations with bitwise-write-enables. This memory is spread around the core logic of the

masterslice and is convenient for matching with Xilinx/Altera block SRAM or for combining into larger

memories for processor cache or scratchpad memory.

© ChipX Inc.

3

CEC034 (9/20/05)

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