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CTM8B54E

EPROM-Based 8-Bit CMOS Microcontroller

CERAMATE TECHNICAL 

CTM8B54E/55E/56E/57E

EPROM-Based 8-Bit CMOS Microcontroller

3.4 RESET

This device may be reset by one of the following ways:

(1) Power-on Reset : At power-up, this device will be kept in a RESET condition for a period of 18ms after

the voltage on MCLR/Vpp pin has reached a logic high level.

(2) MCLR reset (normal operation).

(3) WDT reset (normal operation).

(4) MCLR wake-up (from sleep mode).

(5) WDT wake-up (from sleep mode) : Executing the SLEEP instruction can force this device entering into

sleep mode (power saving mode). While in sleep mode, the WDT is cleared but keeps running. This

device can be awakened by WDT time-out or reset input on MCLR pin.

The contents of registers after reset are listed below:

Address

00h

01h

02h

03h

04h

05h

06h

07h

07h-1Fh

N/A

N/A

N/A

Register

INAR

Timer0

PC

STATUS

FSR

PORTA

PORTB

PORTC

General Purpose Register

Acc

IOST

T0MODE

Power-On Reset

xxxx xxxx

xxxx xxxx

1111 1111

0001 1xxx

1xxx xxxx

---- xxxx

xxxx xxxx

xxxx xxxx

xxxx xxxx

xxxx xxxx

1111 1111

--11 1111

/MCLR or WDT Reset

uuuu uuuu

uuuu uuuu

1111 1111

000# #uuu

1uuu uuuu

---- uuuu

uuuu uuuu

uuuu uuuu

uuuu uuuu

uuuu uuuu

1111 1111

--11 1111

Note: x = unknown, u = unchanged, - = unimplemented, read as “0”,

# = refer to the following table

Condition

/MCLR Reset (not during SLEEP)

/MCLR Reset during SLEEP

WDT Reset (not during SLEEP)

WDT Reset during SLEEP

Status:bit 4

u

1

0

0

Status:bit 3

u

0

1

0

* All specs and applications shown above subject to change without prior notice.

1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C

Email: server@ceramate.com.tw

Tel:886-3-3529445

Fax:886 -3 -3521052

Page 9 of 23

Http: www.ceramate.com.tw

Rev 1.1 Dec 26,2001

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