CS8920A Ver la hoja de datos (PDF) - Cirrus Logic

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CS8920A

Crystal LAN ISA Plug-and-Play Ethernet Controller

Cirrus Logic 

CONTENTS

1.0 INTRODUCTION

1.1 General Description . . . . 4

1.2 System Applications . . . . 5

1.3 Key Features and Benefits . . . 5

1.4 Enhancements Made in CS8920A . 8

2.0 PIN DESCRIPTION

2.1 Pin Diagram . . . . . . 9

2.2 Pin Description . . . . . . 10

3.0 FUNCTIONAL DESCRIPTION

3.1 Overview . . . . . . . 14

3.2 ISA Bus Interface . . . . . 15

3.3 Reset and Initialization . . . . 16

3.4 Plug and Play . . . . . . 18

3.5 Configuration with EEPROM . . 19

3.6 Programming the EEPROM . . 23

3.7 Boot PROM Operation . . . . 24

3.8 Low-Power Modes . . . . . 25

3.9 LED Outputs . . . . . . 26

3.10 Media Access Control (MAC) . . 27

3.11 Encoder/Decoder (ENDEC) . . 33

3.12 10BASE-T Transceiver . . . . 34

3.13 Attachment Unit Interface (AUI) . 37

3.14 External Clock Oscillator . . . 38

4.0 PACKETPAGE ARCHITECTURE

4.1 PacketPage Overview . . . . 39

4.2 PacketPage Memory Map . . . 40

4.3 Bus Interface Registers

Product Identification Code . . 42

DMA Start of Frame . . . . 43

DMA Frame Count . . . . 43

RxDMA Byte Count . . . . 43

EEPROM Command . . . . 44

EEPROM Data . . . . . 44

Receive Frame Byte Counter . . 44

4.4 Status and Control Registers . . 45

4.4.1 Status/Control Bit Definitions 46

4.4.2 Status/Control Register Summary 47

4.5 Status/Control Register Details

(0) Interrupt Status Queue . . 50

(3) Receiver Configuration (RxCFG) 51

(4) Receiver Event (RxEvent) . 52

(5) Receiver Control (RxCTL) . 53

(7) Transmit Configuration (TxCFG) 54

(8) Transmit Event (TxEvent) . 55

(9) Transmit Command (TxCMD) 56

2

CS8920A

(B) Buffer Configuration (BufCFG) 57

(C) Buffer Event (BufEvent) . . 59

(D) Advance Interrupt Control

and Status (ADVintCTL/ST) . 60

(10) Receive Miss Counter (RxMISS) 61

(12) Trans. Collision Count (TxCOL) 61

(13) Line Control (LineCTL) . . 62

(14) Line Status (LineST) . . . 63

(15) Self Control (SelfCTL) . . 64

(16) Self Status (SelfST) . . . 65

(17) Bus Control (BusCTL) . . 66

(18) Bus Status (BusST) . . . 67

(19) Test Control (TestCTL) . . 68

(1C) AUI Time Domain Reflectometer 69

(1D) Auto Negotiation Control

(AutonegCTL) . . 70

(1E) Auto Negotiation Status

(AutonegST) . . 71

4.6 Initiate Transmit Register

Transmit Command (TxCMD) . 72

Transmit Length (TxLength) . . 73

4.7 Address Filter Registers

Logical Address Table (hash table) 74

Individual Address (IEEE address) 74

4.8 Plug n Play Resource Registers . 75

4.9 Receive and Transmit Frame Locations 80

4.10 8 and 16-bit Transfers . . . . 80

4.11 Memory Mode Operation . . . 81

4.12 I/O Space Operation . . . . 83

5.0 OPERATION

5.1 Servicing the Interrupt Status Queue 86

5.2 Basic Receive Operation . . . 88

5.3 Receive Frame Address Filtering . 95

5.4 Rx Missed and Collision Counters . 98

5.5 Receive DMA . . . . . . 98

5.6 Auto-Switch DMA . . . . . 103

5.7 StreamTransfer . . . . . . 106

5.8 Transmit Operation . . . . . 108

5.9 Full Duplex Considerations . . . 115

5.10 System Wakeup with Wakeup Frames 115

6.0 TEST MODES

6.1 Boundary Scan Test . . . . . 121

7.0 ABSOLUTE MAXIMUM RATINGS . 125

Recommended Operating Conditions . 125

8.0 OPERATING CONDITIONS . . . 125

DS238PP2

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