7/31/07
CS5560
SWITCHING CHARACTERISTICS (CONTINUED)
TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%
Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF.
Parameter
Symbol Min
Typ
Max Unit
Serial Port Timing in SSC Mode (SMODE = VL)
RDY falling to MSB stable
t1
-
-2
- MCLKs
Data hold time after SCLK rising
t2
-
10
-
ns
Serial Clock (Out)
(Note 12, 13)
Pulse Width (low) t3
50
-
Pulse Width (high) t4
50
-
-
ns
-
ns
RDY rising after last SCLK rising
t5
-
8
- MCLKs
12. SDO and SCLK will be high impedance when CS is high. In some systems it may require a pull-down resister.
13. SCLK = MCLK/2.
MCLK
RDY
CS
SCLK(o)
SDO
t1
t5
t2
t3
t4
MSB
MSB–1
LSB+1 LSB
Figure 1. SSC Mode - Read Timing, CS remaining low (Not to Scale)
DS713A5
7