CS5560 Ver la hoja de datos (PDF) - Cirrus Logic
Número de pieza
componentes Descripción
Fabricante
CS5560 Datasheet PDF : 32 Pages
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7/31/07
CS5560
SWITCHING CHARACTERISTICS
TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%
Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF.
Parameter
Symbol Min
Typ
Max Unit
Master Clock Frequency
Internal Oscillator XIN
12
14
16
MHz
External Clock fclk
0.5
16
16.2 MHz
Master Clock Duty Cycle
40
-
60
%
Reset
RST Low Time
tres
1
-
-
µs
RST rising to RDY falling
Internal Oscillator twup
External Clock
-
120
-
µs
-
1536
- MCLKs
Calibration
CAL pulse width
(Note 8) tpw
4
-
- MCLKs
CAL high setup time to RST rising
(Note 8) tccw
0
-
-
ns
Calibration Time
RST rising (CAL high) to RDY falling
tscl
-
331458
- MCLKs
Calibration Time
CAL rising (RST high) to RDY falling
tcal
-
331458
- MCLKs
Conversion
CONV Pulse Width
tcpw
4
-
- MCLKs
BP/UP setup to CONV falling
(Note 9)
tscn
0
-
-
ns
CONV low to start of conversion
tscn
-
-
2 MCLKs
Perform Single Conversion (CONV high before RDY falling)
tbus
20
-
- MCLKs
Conversion Time
(Note 10)
Start of Conversion to RDY falling tbuh
-
-
324 MCLKs
Sleep Mode
SLEEP low to low-power state
tcon
SLEEP high to device active (Note 11) tcon
-
50
-
µs
-
3083
- MCLKs
8. CAL can be controlled by the same signal used for RST. If CAL goes high simultaneously with RST, a calibration
will be performed, but CAL must remain high until RDY falls.
9. BP/UP can be changed coincident CONV falling. BP/UP must remain stable until RDY falls.
10. If CONV is held low continuously, conversions occur every 320 MCLK cycles.
If RDY is tied to CONV, conversions will occur every 322 MCLKs.
If CONV is operated asynchronously to MCLK, a conversion may take up to 324 MCLKs.
RDY falls at the end of conversion.
11. RDY will fall when the device is fully operational when coming out of sleep mode.
6
DS713A5
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