CDB53L21 Ver la hoja de datos (PDF) - Cirrus Logic

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Fabricante

CDB53L21

Low Power, Stereo Analog to Digital Converter

Cirrus Logic 

1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE

CS53L21

32 31 30 29 28 27 26 25

LRCK 1

SDA/CDIN (MCLKDIV2) 2

SCL/CCLK (I²S/LJ) 3

AD0/CS (TSTN) 4

VA_PULLUP 5

TSTO 6

AGND 7

TSTO 8

CS53L21

24 AIN1B

23 AIN1A

22 AFILTB

21 AFILTA

20 AIN2B/BIAS

19 AIN2A

18 MICIN2/BIAS/AIN3B

17 MICIN1/AIN3A

9 10 11 12 13 14 15 16

Pin Name

LRCK

SDA/CDIN

(MCLKDIV2)

SCL/CCLK

(I²S/LJ)

AD0/CS

(TSTN)

VA_PULLUP

TSTO

AGND

TSTO

#

Pin Description

1 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

serial audio data line.

Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode. CDIN is the input data line for the

2 control port interface in SPI Mode.

MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry.

Serial Control Port Clock (Input) - Serial clock for the serial control port.

3 Interface Format Selection (Input) - Hardware Mode: Selects between I²S & Left-Justified interface for-

mats for the ADC.

Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode; CS

is the chip-select signal for SPI format.

4

Test In (Input) - Hardware Mode: This pin is an input used for test purposes only and should be tied to

DGND for normal operation.

5 Reference Pull-up (Input) - This pin is an input used for test purposes only and must be pulled-up to VA

using a 47 kΩ resistor.

6 Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-

nection external to the pin).

7 Analog Ground (Input) - Ground reference for the internal analog section.

8 Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-

nection external to the pin).

6

DS700PP1

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