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CS5461A

Single Phase, Bi-directional Power/Energy IC

Cirrus Logic 

CS5461A

E 1 ...

E 2 ...

tedge

P o s itiv e E n e rg y

...

...

N e g a tiv e E n e rg y

Figure 6. Stepper Motor Format on E1 and E2

energy level, the energy output pins (E1 and E2) alter-

nate changing states (see Figure 6). The duration

(tedge) between the alternating states is defined by the

transfer function:

te d g e ( sec )

=

----------1-----------

FREQE

The direction the motor will rotate is determined by the

order of the state changes. When energy is positive, E1

will lead E2. When energy is negative, E2 will lead E1.

The Pulse Width Register (PW) does not affect the step-

per motor format.

5.4.5 Pulse Output E3

The pulse output E3 is designed to assist with meter cal-

ibration. The pulse-output frequency of E3 is directly

proportional to the active power calculated from the in-

put signals. E3 pulse frequency is derived using a sim-

ular transfer function as E1, but is set by the value in the

PulseRateE3 Register.

The E3 pin outputs negative and positive energy, but

has no energy direction indicator.

The pulse width of E3 is configurable. The PulseWidth

register defines the pulse width of E3 in units of 1/OWR

or:

tpw

=

----------P---u---l--s--e---W-----i-d---t--h----------

((MCLK) ⁄ K) ⁄ 1024

The default value is 0.

5.4.6 Anti-creep for the Pulse Outputs

Anti-creep allows the measurement element to maintain

an energy level, such that when the magnitude of the

accumulated active power is below this level, no energy

pulses are output. Anti-creep is enabled by setting bit

FAC in the Control Register for E3 and bit EAC in the

Control Register for E1 and E2.

For low-frequency pulse output formats (i.e. mechanical

counter and stepper motor formats), the active power is

accumulated over time. When a designated energy lev-

el is reached (determined by the transfer function) a

pulse is generated on E1 and/or E2. If active power with

alternating polarity occurs during the accumulation peri-

od (e.g. random noise at zero power levels), the accura-

cy of the registered energy will be maintained.

For high-frequency pulse output formats (i.e. normal

and alternate pulse formats), the active power is accu-

mulated over time until a ±8x buffer is defined. Then,

when the designated energy level is reached, a pulse is

generated on E1 and/or E2. For pulse outputs with high

frequencies and power levels close to zero, the extend-

ed buffer prevents random noise from being registered

as active energy.

5.4.7 Design Examples

EXAMPLE #1:

The maximum rated levels for a power line meter are

250 V rms and 20 A rms. The required number of puls-

es per second on E1 is 100 pulses per second (100 Hz),

when the levels on the power line are 220 V rms and

15 A rms.

With a 10x gain on the voltage and current channel the

maximum input signal is 250 mVP (see Section 5.1 An-

alog Inputs on page 15). To prevent over-driving the

channel inputs, the maximum rated rms input levels will

register 0.6 in VRMS and IRMS by design. Therefore the

voltage level at the channel inputs will be 150 mV rms

when the maximum rated levels on the power lines are

250 V rms and 20 A rms.

Solving for PulseRateE1,2 using the transfer function:

PulseRateE1, 2

=

------F----R-----E----Q-----E------×----V-----R-----E----F----I--N-----2-------

VIN × VGAIN × IIN × PF

Therefore with PF = 1 and

VIN = 220V × ((150mV) ⁄ (250V)) = 132mV

IIN = 15A × ((150mV) ⁄ (20A)) = 112.5mV

the PulseRateE1,2 Register is set to:

PulseRateE = 0----.-1----3---2-----×--1---1-0--0-0----×-×----0-2--.-.-15---1-2---2---5-----×-----1---0-- = 420.8754Hz

18

DS661F2

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