CDB4955 Ver la hoja de datos (PDF) - Cirrus Logic
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CDB4955 Datasheet PDF : 60 Pages
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CS4954 CS4955
NTSC Vertical Timing (odd field)
Line
HSYNC
3
4
5
6
7
8
9
10
VSYNC
FIELD
NTSC Vertical Timing (even field)
Line
HSYNC
264
265
266
267
268
269
270
271
VSYNC
FIELD
Line
HSYNC
PAL Vertical Timing (odd field)
265
1
2
3
4
5
6
7
VSYNC
FIELD
PAL Vertical Timing (even field)
Line
HSYNC
311
312
313
314
315
316
317
318
VSYNC
FIELD
Figure 6. Vertical Timing
VSYNC stays low for 2.5 line-times and transitions a 262 line field (524/525 lines for NTSC). The
high with the beginning of line 315. Video input on common method is flawed: over time, the output
the V [7:0] pins is expected between line 336 display rate will overrun a system-clock-locked
through line 622.
MPEG-2 decompressor and display a field twice
5.2.7 Progressive Scan
every 8.75 seconds.
The CS4954/5 supports a pseudo-progessive scan 5.2.8 NTSC Progressive Scan
mode for which “odd” and “even” numbered line VSYNC will transition low at line four to begin
information is presented in “odd” numbered line field one and will remain low for three lines or
positions by varying the vertical blanking timing. 2574 pixel cycles (858 × 3). NTSC interlaced tim-
This preserves precise MPEG-2 frame rates of 30 ing is illustrated in Figure 9. In this mode, the
and 25 frames per second. This mode is in contrast CS4954/5 expects digital video input at the V [7:0]
to other digital video encoders, which commonly pins for 240 lines beginning on active video line 22
support progressive scan by repetitively displaying and continuing through line 261.
18
DS278F6
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