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CS495313
(Rev.:2008)

32-bit Audio Decoder DSP Family with Dual DSP Engine Technology

Cirrus Logic 

CS4953xx Data Sheet

32-bit Audio Decoder DSP Family

9. Package Mechanical Drawings ..............................................................................................31

9.1 128-pin LQFP Package Drawing ............................................................................................................ 31

9.2 144-Pin LQFP Package Drawing ............................................................................................................ 32

10. Revision History ....................................................................................................................33

List of Figures

Figure 1. RESET Timing ........................................................................................................................................12

Figure 2. XTI Timing ..............................................................................................................................................12

Figure 3. Serial Control Port - SPI Slave Mode Timing ..........................................................................................14

Figure 4. Serial Control Port - SPI Master Mode Timing ........................................................................................15

Figure 5. Serial Control Port - I2C Slave Mode Timing ..........................................................................................16

Figure 6. Serial Control Port - I2C Master Mode Timing ........................................................................................17

Figure 7. Parallel Control Port - Intel® Mode Read Cycle ......................................................................................19

Figure 8. Parallel Control Port - Intel Mode Write Cycle ........................................................................................19

Figure 9. Parallel Control Port - Motorola® Mode Read Cycle Timing ...................................................................21

Figure 10. Parallel Control Port - Motorola Mode Write Cycle Timing ...................................................................21

Figure 11. UART Timing ........................................................................................................................................22

Y Figure 12. Digital Audio Input (DAI) Port Timing Diagram .....................................................................................23

Figure 13. Direct Stream Digital - Serial Audio Input Timing ..................................................................................24

Figure 14. Digital Audio Port Timing, MCLK Master Mode ....................................................................................25

R Figure 15. External Memory Interface - SDRAM Burst Read Cycle .......................................................................26

Figure 16. External Memory Interface - SDRAM Burst Write Cycle .......................................................................26

A Figure 17. External Memory Interface - SDRAM Auto Refresh Cycle ....................................................................27

Figure 18. External Memory Interface - SDRAM Load Mode Register Cycle ........................................................27

Figure 19. 128-Pin LQFP Pin-Out Drawing ............................................................................................................29

IN Figure 20. 144-Pin LQFP Pin-Out Drawing ............................................................................................................30

Figure 21. 128-Pin LQFP Package Drawing .........................................................................................................31

Figure 22. 144-Pin LQFP Package Drawing .........................................................................................................32

List of Tables LIM Table 1. CS4953xx Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 2. Device and Firmware Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. CS495303 DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

E Table 4. CS495313 DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 6. Environmental, Manufacturing, and Handling Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

R Table 7. 128-Pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

PTable 8. 144-Pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

DS705PP3

Copyright 2008 Cirrus Logic

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