CDB4382 Ver la hoja de datos (PDF) - Cirrus Logic
Número de pieza
componentes Descripción
Fabricante
CDB4382 Datasheet PDF : 42 Pages
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CS4382
DSD - SWITCHING CHARACTERISTICS
(For KQZ TA = -10°C to +70°C; Logic 0 = GND; VLS = 1.8 V to 5.5 V; Logic 1 = VLS Volts; CL = 30 pF)
Parameter
Symbol
Master Clock Frequency
(Note 18)
MCLK Duty Cycle
modes)
(All DSD
DSD_SCLK Pulse Width Low
DSD_SCLK Pulse Width High
DSD_SCLK Frequency
pled)
(64x Oversam-
(128x Oversampled)
tsclkl
tsclkh
DSD_L / _R valid to DSD_SCLK rising setup time
DSD_SCLK rising to DSD_L or DSD_R hold time
tsdlrs
tsdh
Min
4.096
40
20
20
1.024
2.048
20
20
Typ Max
-
38.4
50
60
-
-
-
-
-
3.2
-
6.4
-
-
-
-
Unit
MHz
%
ns
ns
MHz
MHz
ns
ns
Note:
18. Min is 4 times 64x DSD or 2 times 128x DSD, and Max is 12 times 64x DSD or 6 times 128x DSD. The
proper MCLK to DSD_SCLK ratio must be set either by the DIF registers or the M0:2 pins
DSD_SCLK
t sclkh
t sclkl
t sdlrs t sdh
DSD_L, DSD_R
Figure 2. Direct Stream Digital - Serial Audio Input Timing
10
DS514F2
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