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CMPWR330SAR Datasheet PDF : 8 Pages
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CALIFORNIA MICRO DEVICES
CMPWR330
Typical Thermal Characteristics
The overall junction to ambient thermal resistance (θJA)
for device power dissipation (PD) consists primarily of
two paths in series. The first path is the junction to the
case (θJC) which is defined by the package style, and the
second path is case to ambient (θCA) thermal resistance
which is dependent on board layout. The final operating
junction temperature for any set of conditions can be
estimated by the following thermal equation:
T
JUNC
=
T
AMB
+
P
D
(θJC
)
+
P
D
(θCA
)
= TAMB + PD (θJA)
The CMPWR330 uses a thermally enhanced package
where all the GND pins (5 through 8) are integral to the
leadframe. When this package is mounted on a double
sided printed circuit board with two square inches of
copper allocated for “heat spreading”, the resulting θJA is
50°C/W.
Based on a maximum power dissipation of 0.7W
(1.75V x 0.4A) with an ambient of 70°C the resulting
junction temperature will be:
TJUNC = TAMB + PD (θJA )
= 70°C + 0.7W (50°C/W)
= 70°C + 35°C = 105°C
Thermal characteristics were measured using a double
sided board with two square inches of copper area
connected to the GND pins for “heat spreading”.
Measurements showing performance up to junction
temperature of 125°C were performed under light load
conditions (5mA). This allows the ambient temperature
to be representative of the internal junction temperature.
Note: The use of multi-layer board construction with
separate ground and power planes will further enhance
the overall thermal performance. In the event of no
copper area being dedicated for heat spreading, a multi-
layer board construction, using only the minimum size
pad layout, will typically provide the CMPWR330 with an
overall θJA of 70°C/W which allows up to 780mW to be
safely dissipated.
3.32
3.31
3.30
3.29
3.28
20
30
40
50
60
70
Temperature (˚C)
Figure 23. VOUT Variation with TAMB (400mA Load)T
4.55
4.50
4.45
VSELECT
4.40
4.35
4.30 VDESELECT
4.25
4.20
25
50
75
100
125
150
Temperature (˚C)
Figure 24. Select/Deselect Threshold Variation with TJUNC
0.37
0.35
0.33
0.31
0.29
0.27
0.25
20
30
40
50
60
70
Temperature (˚C)
Figure 25. VAUX Switch Resistance vs TAMB
©2001 California Micro Devices Corp. All rights reserved. Smart OR™ is a trademark of California Micro Devices.
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214
8
Fax: (408) 263-7846
www.calmicro.com
3/6/2001
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