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CM3132-02SB

Triple Linear Voltage Regulator for DDR-I Memory and CPU

California Micro Devices Corp 

PRELIMINARY

CM3132

Triple Linear Voltage Regulator for DDR-I Memory and CPU

Features

• Fully integrated power solution for a CPU/SOC

core and DDR-I memory ICs

• Lowest system cost and smallest footprint with just

three external output capacitors

• Three linear regulators for VCORE (1.5A), VDDQ

(1.5A), and VTT (0.5A, source-sink)

• VDDQ = 2.5V, VTT = VDDQ/2 ±25mV

• VCORE is adjustable, with a default output of 1.5V

• Over-temperature and reverse current protection

• Overcurrent protection for all regulators

• PSOP-8 package with integrated heat spreader

• Lead-free version available

Applications

• Core CPU and DDR-I memory power for:

− Set Top Boxes, DVD Players, Games

− Digital TVs, Flat Panel Displays

− Printers, Digital Projectors

− Embedded systems

− Communications systems

Product Description

The CM3132 provides an integrated power solution for a

CPU core and DDR-I memory for consumer and other

embedded applications. It features three independent linear

regulators for VCORE, VDDQ and VTT supply regulation. The

default voltage for VCORE is 1.5V. The SENSE_CORE pin

can be tied to GND for the default voltage, or through a

resistor divider for setting the CPU core in the range 1.2V to

1.8V. VDDQ is internally set to 2.50V and the VTT voltage is

always half the VDDQ voltage. A capacitor should be con-

nected to each of the three outputs.

There are two enable pins, EN_CORE and EN_DDR. When

EN_CORE is set high, the CORE regulator is disabled.

When EN_DDR is set high, the two DDR regulators are dis-

abled to minimize overall system power dissipation when

memory is in standby mode. These two enable pins allow

power sequencing of the DDR and CORE regulator blocks

independently.

The CM3132 is available in a PSOP-8 package that has

excellent thermal dissipation. It is available with optional

lead-free finishing.

Typical Application Circuit

2.8V to 3.3V

VCC

CVCC

Enable DDR

Memory #

EN_DDR

Enable CORE#

EN_CORE

VREF

R

R

VDDQ

REGULATOR

VDDQ = 2.5V

VTT

REGULATOR

CDDQ

VREF=1.25V

VTT=1.25V

DDR

MEMORY

CTT

VREF

VCORE

REGULATOR

VCORE

R3

SENSE_CORE R4

CCORE

CPU

CORE

+ I/O

GND

Circuit Schematic

VCC

VREF

EN_DDR

R

R

VDDQ

REGULATOR

VDDQ

VTT

REGULATOR

VTT

EN_CORE

VREF

VCORE

REGULATOR

VCORE

GND

SENSE_CORE

© 2004 California Micro Devices Corp. All rights reserved.

10/13/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 1

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