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CDP1802AC/3

High-Reliability CMOS 8-Bit Microprocessor

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CDP1802AC/3

Timing Waveforms (Continued)

CLOCK

tW 0

00 01

1

10 11

2

20 21

3

30 31

4

40 41

5

50 51

6

60 61

7

0

70 71 00 01

TPA

tPLH

tPHL

TPB

MEMORY

ADDRESS

tPLH, tPHL

tSU

tH

HIGH ORDER tPLH, tPHL

ADDRESS BYTE

LOW ORDER

ADDRESS BYTE

MRD

(MEMORY

READ CYCLE)

MWR

(MEMORY

WRITE CYCLE)

tPLH

tPHL tSU

tPLH

tPHL

tPHL

DATA FROM

CPU TO BUS

tPLH

tPHL

tPLH, tPHL

tH

tPLH

tPLH

tH

tPLH, tPHL

STATE

CODES

tPLH

tPHL

Q

tPLH, tPHL

tPLH, tPHL

N0, N1, N2

(I/O EXECUTION

CYCLE)

DATA FROM

BUS TO CPU

tPLH

DMA

REQUEST

INTERRUPT

REQUEST

EF 1-4

FLAG LINES

SAMPLED (IN S1)

tSU tH

tPLH

DATA

LATCHED IN CPU

tSU

tH

DMA SAMPLED (S1, S2, S3)

tSU

tH

INTERRUPT

SAMPLED (S1, S2)

tSU

tH

WAIT

CLEAR

tSU

tW

ANY NEGATIVE

TRANSITION

FIGURE 2. TIMING WAVEFORM

NOTES:

8. This timing diagram is used to show signal relationships only and does not represent any specific machine cycle.

9. All measurements are referenced to 50% point of the waveforms.

10. Shaded areas indicate “Don’t Care” or undefined state. Multiple transitions may occur during this period.

FN1441 Rev 3.00

October 17, 2008

Page 8 of 27

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