CA3060 Ver la hoja de datos (PDF) - Harris Semiconductor
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CA3060 Datasheet PDF : 12 Pages
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CA3060
4. Calculation of Bias Resistance. For minimum supply
0
current drain the amplifier bias current IABC should be fed
directly from the supplies and not from the bias regulator.
The value of the resistor RABC may be directly calculated
-20
using Ohm’s law.
RL = 10kΩ
CL = 0
RABC = V-----S----U----PI--A---–B----CV----A-----B----C--
RABC = 2-1---02-----×–-----10---0.--6-–--3-6--
RABC = 568.5kΩ or ≅ 560kΩ
5. Calculation of Offset Adjustment Circuit. In order to
reduce the loading effect of the offset adjustment circuit
on the power supply, the offset control should be
arranged to provide the necessary offset current. The
source resistance of the non-inverting input is made
equal to the source resistance of the inverting input,
i.e., 2-2---00----kk---ΩΩ------+×-----22---0-0---00----kk---ΩΩ--- ≅ 18kΩ
-40
-60
RL = 10kΩ
CL = 15pF
-80
0.01
0.1
1.0
10
100
FREQUENCY (MHz)
FIGURE 20. EFFECT OF CAPACITIVE LOADING ON
FREQUENCY RESPONSE
1000
AB C D
E
F
G
H
Because the maximum offset voltage is 5mV plus an
100
I
additional increment due to the offset current (Figure 2)
J
flowing through the source resistance (i.e., 200 x 10-9 x
18 x 103V), the Offset Voltage Range = 5mV + 3.6mV =
10
K
±8.6mV. The current necessary to provide this offset is:
L
8--1--.-8-6---km----Ω--V-- ≅ 0.48µA
1
With a supply voltage of ±6V, this current can be
provided by a 10MΩ resistor. However, the stability of
such a resistor is often questionable and a more realistic
value of 2.2MΩ was used in the final circuit.
Capacitance Effects
The CA3060 is designed to operate at such low power levels
that high impedance circuits must be employed. In designing
such circuits, particularly feedback amplifiers, stray circuit
capacitance must always be considered because of its
adverse effect on frequency response and stability. For
example a 10kΩ load with a stray capacitance of 15pF has a
time constant of 1MHz. Figure 20 illustrates how a 10kΩ
15pF load modifies the frequency characteristic.
Capacitive loading also has an effect on slew rate; because
the peak output current is established by the amplifier bias
current, IABC (Figure 5), the maximum slew rate is limited to
the maximum rate at which the capacitance can be charged
by the IOM. Therefore, SR = dv/dt = IOM/CL, where CL is the
total load capacitance including strays. This relationship is
shown graphically in Figure 21. When measuring slew rate
for this data sheet, care was taken to keep the total
capacitive loading to 13pF.
0.01
0.1
1.0
10
100
SLEW RATE (V/µs)
A. CL = 10,000pF
B. CL = 3,000pF
C. CL = 1000pF
D. CL = 300pF
E. CL = 100pF
F. CL = 30pF
G. CL = 10pF
H. CL = 3pF
I. CL = 1pF
J. CL = 0.3pF
K. CL = 0.1pF
L. CL = 0.03pF
FIGURE 21. EFFECT OF LOAD CAPACITANCE ON SLEW RATE
Phase Compensation
In many applications phase compensation will not be
required for the amplifiers of the CA3060. When needed,
compensation may easily be accomplished by a simple RC
network at the input of the amplifier as shown in Figure 17.
The values given in Figure 17 provide stable operation for
the critical unity gain condition, assuming that capacitive
loading on the output is 13pF or less. Input phase compen-
sation is recommended in order to maintain the highest
possible slew rate.
In applications such as integrators, two OTAs may be
cascaded to improve current gain. Compensation is best
accomplished in this case with a shunt capacitor at the
output of the first amplifier. The high gain following compen-
sation assures a high slew rate.
3-8
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