CA1391 Ver la hoja de datos (PDF) - Harris Semiconductor

Número de pieza

componentes Descripción

Fabricante

CA1391

TV Horizontal Processors

Harris Semiconductor 

CA1391, CA1394

Application Information

Circuit Operation (See Schematic Diagram)

The CA1391 and CA1394 contain the oscillator, phase

detector, and predriver sections necessary for the television

horizontal oscillator and AFC loop.

The oscillator is an RC type with Terminal 7 used to control the

timing. If it is assumed that Q7 is initially off, then an external

capacitor connected from Terminal 7 to ground charges through

an external resistance connected between Terminals 6 and 7. As

soon as the voltage at Terminal 7 exceeds the potential set at the

base of Q8 by resistors R11 and R12, Q7 turns on, and Q6 sup-

plies base current to Q5 and Q10. Transistor Q5 discharges the

capacitor through R4 until the base bias of Q7 falls below that of

Q8 at which time, Q7 turns off, and the cycle repeats.

The sawtooth generated at the base of Q4 appears across R3

and turns off Q3 whenever the sawtooth voltage rises to a value

that exceeds the bias set at Terminal 8. By adjusting the poten-

tial at Terminal 8, the duty cycle at the pre-drive output (Termi-

nal 1) may be changed. The phase detector is isolated from the

remainder of the circuit by R31, Z2, Q15 and Q16. The phase

detector consists of the comparator Q22 and Q23, and the

gated current source Q18. Negative going sync pulses at Ter-

minal 3 turn off Q17, and the current division between Q22 and

Q23 is then determined by the phase relationship of the sync

and the sawtooth waveform at Terminal 4, which is derived from

the horizontal flyback pulse. If there is no phase difference

between the sync and sawtooth, equal currents flow in the col-

lectors of Q22 and Q23 during each half of the sync pulse

period. The current in Q22 is turned around by current mirror

Q20 and Q21 so that there is no net output current at Terminal 5

for balanced conditions. When a phase offset occurs, current

flows either in or out of Terminal 5. In circuit applications, this

terminal is connected to Terminal 7 through an external low

pass filter, thereby controlling the oscillator.

Shunt regulation for the circuit is obtained by using a VBE

and zener multiplier. Resistors R13 and R14 multiply the VBE

of Q11, and the ratio of R15 and R16 multiplies the voltage of

the zener diode Z1.

5.0 TA = 25oC

FREE RUNNING FREQUENCY = 15734Hz

4.5

4.0

3.5

3.0

2.5

2.0

0

10

20

30

40

50

60

70

POSITIVE PULSE WIDTH AT TERMINAL 1 (µs)

FIGURE 2. DUTY CYCLE AT THE PRE-DRIVE OUTPUT (TERMINAL

1) AS IT IS AFFECTED BY THE INPUT AT TERMINAL 8

V+ 24V

620Ω

3kΩ

+150V

4kΩ

10W

6800pF

120kΩ

2.4kΩ

2

2.7kΩ

14kΩ

470µF

0.47µF

8.2kΩ

0.001µF

8

1.5kΩ

1

270Ω

0.0027µF

150kΩ

7

6

CA1394

2

3

470pF

7.5kΩ

0.01µF

5

4

0.1µF

390kΩ

22Ω

0.1µF

3.9kΩ

SYNC

1.2kΩ

20VP-P

5µs

60VP-P

10µs

FIGURE 3. TYPICAL CIRCUIT APPLICATION

8-12

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