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C8051F018-GQ Datasheet PDF : 2 Pages
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C8051F018
25 MIPS, 16 kB Flash, 10-Bit ADC, 64-Pin Mixed-Signal MCU
Analog Peripherals
10-Bit ADC
- ±1 LSB INL; no missing codes
- Programmable throughput up to 100 ksps
- 8 external inputs; programmable as single-ended or differential
- Data-dependent windowed interrupt generator
- Built-in temperature sensor (±3 °C)
Two Comparators
- 16 programmable hysteresis values
- Configurable to generate interrupts or reset
Internal Voltage Reference
VDD Monitor/Brown-out Detector
On-Chip JTAG Debug & Boundary Scan
- On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
- Provides breakpoints, single stepping, watchpoints, stack monitor
- Inspect/modify memory and registers
- Superior performance to emulation systems using ICE-chips, target
pods, and sockets
- IEEE1149.1 compliant boundary scan
Supply Voltage: 2.8 to 3.6 V
- Typical operating current: 12.5 mA at 25 MHz
- Multiple power saving sleep and shutdown modes
Temperature Range: –40 to +85 °C
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
- Up to 25 MIPS throughput with 25 MHz system clock
- Expanded interrupt handler
Memory
- 1280 bytes data RAM
- 16 kB Flash; in system programmamble in 512-byte sectors (512 bytes
are reserved)
Digital Peripherals
- 32 port I/O; all are 5 V tolerant
- Hardware SMBus™ (I2C™ compatible), SPI™, and UART serial ports
available concurrently
- Programmable 16-bit counter/timer array with five capture/compare
modules
- 4 general-purpose 16-bit counter/timers
- Dedicated watchdog timer; bidirectional reset
Clock Sources
- Internal programmable oscillator: 2–16 MHz
- External oscillator: Crystal, RC, C, or Clock
- Can switch between clock sources on-the-fly
Package
- 64-pin TQFP (standard lead and lead-free packages)
Ordering Part Numbers
- Lead-free package: C8051F018-GQ
- Standard package: C8051F018
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AV+
AGND
AGND
TCK
TMS
TDI
TDO
RST
XTAL1
XTAL2
VREF
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
CP0+
CP0-
CP1+
CP1-
Digital Power
Analog Power
JTAG Boundary Scan
Logic Debug HW
VDD
Monitor
WDT
8
0
5 Reset
1
External
Oscillator
Circuit
Internal
Oscillator
C
o System Clock
r
e
VREF
16 kB
FLASH
256 Byte
RAM
1024 Byte
XRAM
SFR Bus
A
M
U
X
CP0
TEMP
SENSOR
CP1
ADC
100 ksps
(10-Bit)
UART
C
SMBus
R
SPI Bus
O
S
5-Chnl
S
PCA
B
Timers
A
0,1,2
R
Timer 3
S
Port 0
Latch
W
I
Port 1
Latch
T
C
Port 2
H
Latch
Port 3
Latch
Precision Mixed Signal
Copyright © 2005 by Silicon Laboratories
P
P0.0
0
P0.1
P0.2
P0.3
D
P0.4
r
v
P0.5
P0.6
P0.7
P
P1.0
P1.1
1
P1.2
P1.3
D
P1.4
r
P1.5
v
P1.6
P1.7
P
2
P2.0
P2.1
P2.2
P2.3
D
P2.4
r
P2.5
v
P2.6
P2.7
P
3
P3.0
P3.1
P3.2
P3.3
D
P3.4
r
P3.5
v
P3.6
P3.7
NC
NC
5.5.2005
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