74LV161DB Ver la hoja de datos (PDF) - Philips Electronics
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74LV161DB Datasheet PDF : 16 Pages
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Philips Semiconductors
Presettable synchronous 4-bit binary counter;
asynchronous reset
Product specification
74LV161
AC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
WAVEFORM
CONDITION
Hold time
th
Dn, PE, CEP, CET to Figures 4 – 6
CP
VCC(V)
1.2
2.0
2.7
3.0 to 3.6
fmax
Maximum clock
pulse frequency
Figures 1, 6
2.0
2.7
3.0 to 3.6
NOTES:
1. Unless otherwise stated, all typical values are measured at Tamb = 25°C
2. Typical values are measured at VCC = 3.3 V.
LIMITS
–40 to +85 °C
MIN TYP1 MAX
–35
0
–12
0
–9
0
–72
14
40
19
58
24
70
–40 to +125 °C
MIN MAX
0
0
0
12
16
20
UNIT
ns
MHz
AC WAVEFORMS
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V;
VOL and VOH are the typical output voltage drop that occur with the output load.
1/fmax
VI
CP INPUT
GND
VOH
Qn, TC
OUTPUT
VOL
VM
tW
tPHL
VM
tPLH
SV00576
Figure 1. Clock (CP) to outputs (Qn, TC) propagation delays,
the clock pulse width and the maximum clock frequency.
VI
CET INPUT
VM
GND
VOH
TC OUTPUT
VOL
tPLH
VM
tPHL
SV00578
Figure 3. Input (CET) to output (TC) propagation delays.
VI
VI
MR INPUT
GND
VI
VM
tW
trem
CP INPUT
GND
VOH
Qn , TC
OUTPUT
VOL
VM
tPHL
VM
SV00577
Figure 2. Master reset (MR) pulse width,
the master reset to output (Qn, TC) propagation delays
and the master reset to clock (CP) removal times.
PE INPUT
VM
GND
VI
tsu
th
tsu
th
CP INPUT
VM
GND
VI
tsu
th
tsu
th
Dn INPUT
VM
GND
The shaded areas indicate when the input is permitted to change
for predictable output performance.
SV00579
Figure 4. Set-up and hold times for input (Dn)
and parallel enable input (PE).
1997 May 15
9
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