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Fabricante

SAA5667

Enhanced TV microcontrollers with On-Screen Display (OSD)

Philips Electronics 

Philips Semiconductors

Enhanced TV microcontrollers with

On-Screen Display (OSD)

Product specification

SAA56xx

SYMBOL

PIN TYPE

DESCRIPTION

G

47

O pixel rate output of the GREEN colour information

R

48

O pixel rate output of the RED colour information

VDS

52

O video/data switch push-pull output for dot rate fast blanking

HSYNC

53

I Schmitt triggered input for a TTL-level version of the horizontal sync pulse;

the polarity of this pulse is programmable by register bit TXT1.H POLARITY.

VSYNC

55

I Schmitt triggered input for a TTL-level version of the vertical sync pulse; the

polarity of this pulse is programmable by register bit TXT1.V POLARITY.

VSSP

VDDC

OSCGND

12, 60

63

69

− periphery ground

− +3.3 V core power supply

− crystal oscillator ground

XTALIN

70

I 12 MHz crystal oscillator input

XTALOUT

71

O 12 MHz crystal oscillator output

RESET

72

I If the reset input is LOW for at least 24 crystal oscillator periods while the

oscillator is running, the device is reset (internal pull-up).

RESET

VDDP

P1.0/INT1

73

I If the reset input is HIGH for at least 24 crystal oscillator periods while the

oscillator is running, the device is reset. This pin should be connected to

VDDC via a capacitor if an active HIGH reset is required (internal pull-down).

75

− +3.3 V periphery power supply

76

I/O Port 1. 8-bit programmable bidirectional port with alternative functions.

P1.1/T0

P1.2/INT0

P1.3/T1

P1.6/SCL0

P1.7/SDA0

P1.4/SCL1

78

I/O P1.0/INT1 is external interrupt 1 which can be triggered on the rising and

79

I/O falling edge of the pulse; P1.1/T0 is Timer/counter 0; P1.2/INT0 is external

80

I/O interrupt 0; P1.3/T1 is Timer/counter 1; P1.6/SCL0 is the serial clock input

81

I/O

for the I2C-bus; P1.7/SDA0 is the serial data port for the I2C-bus; P1.4/SCL1

is the serial clock input for the I2C-bus; P1.5/SDA1 is the serial data port for

82

I/O the I2C-bus.

83

I/O

P1.5/SDA1

84

I/O

RD

9

O read control signal to external data memory

WR

10

O write control signal to external data memory

EA

14

I Control signal used to select external (LOW) or internal (HIGH) program

memory (internal pull-up).

PSEN

19

O enable signal for external program memory

ALE

20

O external latch enable signal; active HIGH

AD0 to AD7

85 to 92 I/O address lines A0 to A7 multiplexed with data lines D0 to D7.

A0 to A7

49, 40, 39,

38, 27, 26,

23, 15

O address lines A0 to A7

A8 to A14

67 to 64,

37, 36, 8

O address lines A8 to A14

A15_LN to A17_LN 7, 77, 3 O address lines A15 to A17; note 1

MOVX_WR

68

O MOVX Write for Hitex 80C51 emulation (internal MOVX Write instruction)

MOVX_RD

74

O MOVX Read for Hitex 80C51 emulation (internal MOVX Read instruction)

2001 Dec 13

8

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