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SAA7391H

ATAPI CD-R block encoder/decoder

Philips Electronics 

Philips Semiconductors

ATAPI CD-R block encoder/decoder

Objective specification

SAA7391

CONTENTS

1

2

2.1

2.2

2.3

2.4

2.5

2.6

3

4

5

6

6.1

7

7.1

7.1.1

7.2

7.2.1

7.3

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

7.4

7.4.1

7.4.2

7.4.3

7.5

7.5.1

7.5.2

7.5.3

7.5.4

7.5.5

7.5.6

7.5.7

7.5.8

7.5.9

7.5.10

FEATURES

GENERAL DESCRIPTION

Memory mapped control registers

Error correction features

Host interface features

Buffer memory organisation

Subcode handling features

Multimedia output audio control features

QUICK REFERENCE DATA

ORDERING INFORMATION

BLOCK DIAGRAM

PINNING

Detailed description of pin functions

FUNCTIONAL DESCRIPTION

Memory field description

DVD-ROM memory field information

CD input control registers

Registers associated with data in process

Multimedia output interface

Subcode input block

Subcode mode transmit control register

General description of the multimedia output

interface

IEC 958/EBU output

Memory-to-memory block copy function

Interrupt registers

Interrupt 1

Interrupt 2

UART interrupt

Host interface

Introduction

Description of the host interface block

Description of the host interface registers

Transfer counter

Packet size store

Sequencer status

Host interface DMA special bits

Automatic block pointer reload programming

DMA transfer programming of the host

interface

Generic interface operation

7.5.11

7.5.12

7.5.13

7.6

7.6.1

7.6.2

7.7

7.7.1

7.7.2

7.7.3

7.8

7.8.1

7.9

7.9.1

7.10

7.10.1

7.10.2

7.10.3

8

9

10

11

11.1

11.2

11.2.1

11.2.2

11.2.3

11.2.4

11.3

11.4

12

13

14

15

15.1

15.2

15.3

15.4

16

17

DMA transfers in generic mode

Normal DMA mode

Burst DMA mode using multiplexed bus

configuration

Microcontroller interface

Kernel based firmware

16-bit registers automatic read and write

8051 CPU and memory management functions

Sub-CPU bus access timing

Buffer memory organisation

Subpage

External memory interface

DRAM interface configuration register

UART for communication with CD engine

UART basic engine interface

Clock generation control

Crystal oscillator

Sub-CPU clock control register

SAA7391 system clock control registers

LIMITING VALUES

THERMAL CHARACTERISTICS

CHARACTERISTICS

TIMING CHARACTERISTICS

External memory interface timing

Host interface timing

Host interface ATAPI PIO and DMA timing

ATA bus timing

Ultra DMA operation and timing

Ultra DMA read/write timing

Sub-CPU interface timing

UART timing

APPENDIX A

APPLICATION INFORMATION

PACKAGE OUTLINE

SOLDERING

Introduction

Reflow soldering

Wave soldering

Repairing soldered joints

DEFINITIONS

LIFE SUPPORT APPLICATIONS

1997 Aug 01

2

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