WS7106CPL Ver la hoja de datos (PDF) - Wing Shing International Group
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WS7106CPL Datasheet PDF : 14 Pages
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Detailed Description
Analog Section
Figure 3 shows the Analog Section for the WS7106 and
WS7107. Each measurement cycle is divided into three
phases. They are (1) auto-zero (A-Z), (2) signal integrate
(INT) and (3) de-integrate (DE).
Auto-Zer o Phase
During auto-zero three things happen. First, input high and
low are disconnected from the pins and internally shorted to
analog COMMON. Second, the reference capacitor is
charged to the reference voltage. Third, a feedback loop is
closed around the system to charge the auto-zero capacitor
CAZ to compensate for offset voltages in the buffer amplifier,
integrator, and comparator. Since the comparator is included
in the loop, the A-Z accuracy is limited only by the noise of
the system. In any case, the offset referred to the input is
less than 10µV.
Signal Integrate Phase
During signal integrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and low
are connected to the external pins. The converter then
integrates the differential voltage between IN HI and IN LO
for a fixed time. This differential voltage can be within a wide
common mode range: up to 1V from either supply. If, on the
other hand, the input signal has no return with respect to the
converter power supply, IN LO can be tied to analog
COMMON to establish the correct common mode voltage. At
WS7106 / WS7107
the end of this phase, the polarity of the integrated signal is
determined.
De-Integrate Phase
The final phase is de-integrate, or reference integrate. Input
low is internally connected to analog COMMON and input
high is connected across the previously charged reference
capacitor. Circuitry within the chip ensures that the capacitor
will be connected with the correct polarity to cause the
integrator output to return to zero. The time required for the
output to return to zero is proportional to the input signal.
Specifically the digital reading displayed is:
DISPLAY
COUNT
=
1000
V---V--R---I-EN----F-
.
Differential Input
The input can accept differential voltages anywhere within the
common mode range of the input amplifier, or specifically from
0.5V below the positive supply to 1V above the negative sup-
ply. In this range, the system has a CMRR of 86dB typical.
However, care must be exercised to assure the integrator out-
put does not saturate. A worst case condition would be a large
positive common mode voltage with a near full scale negative
differential input voltage. The negative input signal drives the
integrator positive when most of its swing has been used up
by the positive common mode voltage. For these critical appli-
cations the integrator output swing can be reduced to less
than the recommended 2V full scale swing with little loss of
accuracy. The integrator output can swing to within 0.3V of
either supply without loss of linearity.
STRAY
CREF
STRAY
CREF+ REF HI
34
36
V+
REF LO CREF -
35
33
RINT
BUFFER V+
28
1
31
IN HI
10µA
INT
A-Z
32
COMMON
A-Z
DE-
DE+
A-Z
DE+
DE-
-
+
INPUT
HIGH
2.8V
N
-
+
INT
30
IN LO
A-Z AND DE(±)
CAZ
A-Z
29
CINT
INT
27
INTEGRATOR
+-
-
+
6.2V
A-Z
COMPARATOR
INPUT
LOW
V-
FIGURE 3. ANALOG SECTION OF WS7106 AND WS7107
TO
DIGITAL
SECTION
5
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