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CY7C43683AV-10AC

3.3V 1K/4K/16K x36 Unidirectional Synchronous FIFO with Bus Matching

Cypress Semiconductor 

CY7C43663AV

CY7C43643AV

CY7C43683AV

Bus Sizing

The Port B bus can be configured in a 36-bit long-word, 18-bit

word, or 9-bit byte format for data read from FIFO. The levels

applied to the Port B Bus Size Select (SIZE) and the Bus

Match Select (BM) determine the Port B bus size. These levels

should be static throughout FIFO operation. Both bus size

selections are implemented at the completion of Master Reset,

by the time the Full/Input Ready flag is set HIGH.

Two different methods for sequencing data transfer are

available for Port B when the bus-size selection is either byte

or word size. They are referred to as Big Endian (most signif-

icant byte first) and Little Endian (least significant byte first).

The level applied to the Big Endian Select (BE) input during

the LOW-to-HIGH transition of MRS1/MRS2 selects the

endian method that will be active during FIFO operation. BE is

a don’t care input when the bus size selected for Port B is

long-word. The endian method is implemented at the

completion of Master Reset, by the time the Full/Input Ready

flag is set HIGH.

Only 36-bit long-word data is written to the FIFO memory on

the CY7C436X3AV. Bus-matching operations are done after

data is read from the FIFO. These bus-matching operations

are not available when transferring data via mailbox registers.

Furthermore, both the word- and byte-size bus selections limit

the width of the data bus that can be used for mail register

operations. In this case, only those byte lanes belonging to the

selected word- or byte-size bus can carry mailbox data. The

remaining data outputs will be indeterminate. The remaining

data inputs will be don’t care inputs. For example, when a

word-size bus is selected, then mailbox data can be trans-

mitted only between A0–17 and B0–17. When a byte-size bus is

selected, then mailbox data can be transmitted only between

A0–8 and B0–8.

Bus-Matching FIFO Reads

Data is read from the FIFO RAM in 36-bit long-word incre-

ments. If a long-word bus size is implemented, the entire long-

word immediately shifts to the FIFO output register. If byte or

word size is implemented on Port B, only the first one or two

bytes appear on the selected portion of the FIFO output

register, with the rest of the long-word stored in auxiliary

registers. In this case, subsequent FIFO reads output the rest

of the long-word to the FIFO output register.

When reading data from the FIFO in the byte or word format,

the unused B9–35 or B18–35 outputs are indeterminate.

Retransmit (RT)

The retransmit feature is beneficial when transferring packets

of data. It enables the receipt of data to be acknowledged by

the receiver and retransmitted if necessary. Retransmit

function applies to CY standard mode only.

The number of 36-/18-/9-bit words written into the FIFO should

be less than full depth minus 2/4/8 words between the reset of

the FIFO (master or partial) and Retransmit setup. A LOW

pulse on RT resets the internal Read pointer to the first phys-

ical location of the FIFO. CLKA and CLKB may be free running

but ENB must be disabled during and tRTR after the retransmit

pulse. With every valid Read cycle after retransmit, previously

accessed data is read and the Read pointer is incremented

until it is equal to the Write pointer. Flags are governed by the

relative locations of the Read and Write pointers and are up-

dated during a retransmit cycle. Data written to the FIFO after

activation of RT are transmitted also. The full depth of the FIFO

can be repeatedly retransmitted.

Document #: 38-06024 Rev. *C

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