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CY7C43643AV

3.3V 1K/4K/16K x36 Unidirectional Synchronous FIFO with Bus Matching

Cypress Semiconductor 

CY7C43663AV

CY7C43643AV

CY7C43683AV

Write if the clock transition occurs at time tSKEW1 or greater

after the Write. Otherwise, the subsequent clock cycle will be

the first synchronization cycle.

Full/Input Ready Flags (FF/IR)

This is a dual-purpose flag. In FWFT Mode, the Input Ready

(IR) function is selected. In CY Standard mode, the Full Flag

(FF) function is selected. For both timing modes, when the

Full/Input Ready flag is HIGH, a memory location is free in the

SRAM to receive new data. No memory locations are free

when the Full/Input Ready flag is LOW and any writes to the

FIFO are ignored.

The Full/Input Ready flag of a FIFO is synchronized to CLKA.

For both FWFT and CY Standard modes, each time a word is

written to a FIFO, its Write pointer is incremented. The state

machine that controls a Full/Input Ready flag monitors a Write

pointer and Read pointer comparator that indicates when the

FIFO SRAM status is full, full – 1, or full – 2. From the time a

word is read from a FIFO, its previous memory location is

ready to be written to in a minimum of two cycles of the

Full/Input Ready flag synchronizing clock. Therefore, a

Full/Input Ready flag is LOW if less than two cycles of the

Full/Input Ready flag synchronizing clock have elapsed since

the next memory Write location has been read. The second

LOW-to-HIGH transition on the Full/Input Ready flag synchro-

nizing clock after the Read sets the Full/Input Ready flag

HIGH.

A LOW-to-HIGH transition on a Full/Input Ready flag synchro-

nizing clock begins the first synchronization cycle of a Read if

the clock transition occurs at time tSKEW1 or greater after the

Read. Otherwise, the subsequent clock cycle can be the first

synchronization cycle.

Almost Empty Flags (AE)

The Almost Empty flag of the FIFO is synchronized to port B

clock. The state machine that controls an Almost Empty flag

monitors a Write pointer and Read pointer comparator that

indicates when the FIFO SRAM status is almost empty, almost

empty + 1, or almost empty + 2. The Almost Empty state is

defined by the contents of register X for AE. These registers

are loaded with preset values during a FIFO reset,

programmed from Port A, or programmed serially (see Almost

Empty flag and Almost Full flag offset programming above). An

Almost Empty flag is LOW when its FIFO contains X or less

words and is HIGH when its FIFO contains (X + 2) or more

words.[2]

The Almost Empty flag is set HIGH by the first CLKB rising

edge after two FIFO writes that fills memory to the (X + 2) level.

A LOW-to-HIGH transition of CLKB begins the first synchroni-

zation cycle if it occurs at time tSKEW2 or greater after the Write

that fills the FIFO to (X + 2) words. Otherwise, the subsequent

synchronizing clock cycle will be the first synchronization

cycle.

Almost Full Flags (AF)

The Almost Full flag of the FIFO is synchronized to port A

clock. The state machine that controls an Almost Full flag

monitors a Write pointer and Read pointer comparator that

indicates when the FIFO SRAM status is almost full, almost

full – 1, or almost full – 2. The Almost Full state is defined by

the contents of register Y for AF. These registers are loaded

with preset values during a FIFO reset, programmed from Port

A, or programmed serially (see Almost Empty flag and Almost

Full flag offset programming above). An Almost Full flag is

LOW when the number of words in its FIFO is greater than or

equal to (1024 – Y), (4096 – Y), or (16384 – Y), for the

CY7C436X3AV respectively. An Almost Full flag is HIGH when

the number of words in its FIFO is less than or equal to

[1024 – (Y + 2)], [4096 – (Y + 2)], or [16384 – (Y + 2)], for the

CY7C436X3AV respectively.

The Almost Full flag is set HIGH by the first CLKA rising edge

after two FIFO reads that reduces the number of words in

memory to [1024/4096/16384 – (Y + 2)]. A LOW-to-HIGH

transition of CLKA begins the first synchronization cycle if it

occurs at time tSKEW2 or greater after the Read that reduces

the number of words in memory to [1024/4096/16384 –

(Y + 2)]. Otherwise, the subsequent synchronizing clock cycle

will be the first synchronization cycle.

Mailbox Registers

Each FIFO has a 36-bit bypass register to pass command and

control information between Port A and Port B without putting

it in queue. The Mailbox Select (MBA, MBB) inputs choose

between a mail register and a FIFO for a port data transfer

operation. The usable width of both the Mail1 and Mail2

registers matches the selected bus size of Port B.

A LOW-to-HIGH transition on CLKA writes A0-35 data to the

Mail1 Register when a Port A Write is selected by CSA, W/RA,

and ENA with MBA HIGH. If the selected Port A bus size is

also 36 bits, then the usable width of the Mail1 Register

employs data lines A0-35. If the selected Port A bus size is 18

bits, then the usable width of the Mail1 Register employs data

lines A0-17. (In this case, A18-35 are don’t care inputs.) If the

selected Port A bus size is 9 bits, then the usable width of the

Mail1 Register employs data lines A0–8. (In this case, A9-35 are

“Don’t Care” inputs.)

A LOW-to-HIGH transition on CLKB writes B0-35 data to the

Mail2 Register when a Port B Write is selected by CSB, W/RB,

and ENB with MBB HIGH. If the selected Port B bus size is

also 36 bits, then the usable width of the Mail2 Register

employs data lines B0–35. If the selected Port B bus size is 18

bits, then the usable width of the Mail2 Register employs data

lines B0–17. (In this case, B18–35 are don’t care inputs.) If the

selected Port B bus size is 9 bits, then the usable width of the

Mail2 Register employs data lines B0-8. (In this case, B9-35 are

“Don’t Care” inputs.)

Writing data to a mail register sets its corresponding flag

(MBF1 or MBF2) LOW. Attempted writes to a mail register are

ignored while the mail flag is LOW.

When data outputs of a port are active, the data on the bus

comes from the FIFO output register if the port Mailbox Select

input is LOW and from the mail register if the port Mailbox

Select input is HIGH.

The Mail1 Register flag (MBF1) is set HIGH by a

LOW-to-HIGH transition on CLKB when a Port B Read is

selected by CSB, W/RB, and ENB with MBB HIGH.

The Mail2 Register flag (MBF2) is set HIGH by a

LOW-to-HIGH transition on CLKA when a Port A Read is

selected by CSA, W/RA, and ENA with MBA HIGH.

The data in a mail register remains intact after it is read and

changes only when new data is written to the register. The

Endian Select feature has no effect on the mailbox data.

Document #: 38-06024 Rev. *C

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