CY7C43643AV Ver la hoja de datos (PDF) - Cypress Semiconductor

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Fabricante

CY7C43643AV

3.3V 1K/4K/16K x36 Unidirectional Synchronous FIFO with Bus Matching

Cypress Semiconductor 

CY7C43663AV

CY7C43643AV

CY7C43683AV

Pin Definitions

Signal Name Description I/O

Function

A0–35

AE

Port A Data

Almost Empty

Flag (Port B)

I 36-bit unidirectional data port for side A.

O Programmable Almost Empty flag synchronized to CLKB. It is LOW when the

number of words in the FIFO is less than or equal to the value in the Almost Empty offset

register, X.[2]

AF

Almost Full Flag O Programmable Almost Full flag synchronized to CLKA. It is LOW when the number

of empty locations in the FIFO is less than or equal to the value in the Almost Full offset

register, Y.[2]

B0–35

BE/FWFT

Port B Data

O 36-bit unidirectional data port for side B.

Big

I This is a dual-purpose pin. During Master Reset, a HIGH on BE will select Big Endian

Endian/First-Wor

operation. In this case, depending on the bus size, the most significant byte or word on

d Fall-Through

Port A is transferred to Port B first. A LOW on BE will select Little Endian operation. In

Select

this case, the least significant byte or word on Port A is transferred to Port B first. After

Master Reset, this pin selects the timing mode. A HIGH on FWFT selects CY Standard

mode, a LOW selects First-Word Fall-Through Mode. Once the timing mode has been

selected, the level on FWFT must be static throughout device operation.

BM

Bus Match

I A HIGH on this pin enables either byte or word bus width on Port B, depending on

Select (Port B)

the state of SIZE. A LOW selects long-word operation. BM works with SIZE and BE to

select the bus size and endian arrangement for Port B. The level of BM must be static

throughout device operation.

CLKA

Port A Clock

I CLKA is a continuous clock that synchronizes all data transfers through Port A

and can be asynchronous or coincident to CLKB. FF/IR and AF are all synchronized to

the LOW-to-HIGH transition of CLKA.

CLKB

Port B Clock

I CLKB is a continuous clock that synchronizes all data transfers through Port B

and can be asynchronous or coincident to CLKA. EF/OR and AE are synchronized to

the LOW-to-HIGH transition of CLKB.

CSA

Port A Chip

Select

I CSA must be LOW to enable a LOW-to HIGH transition of CLKA to read (from Mail2

register) or write on Port A. The A0–35 outputs are in the high-impedance state when

CSA is HIGH.

CSB

Port B Chip

Select

I CSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write

(into Mail2 register) on Port B. The B0–35 outputs are in the high-impedance state when

CSB is HIGH.

EF/OR

Empty/Output

Ready Flag (Port

B)

O This is a dual-function pin. In the CY Standard mode, the EF function is selected. EF

indicates whether or not the FIFO memory is empty. In the FWFT mode, the OR function

is selected. OR indicates the presence of valid data on B0–35 outputs, available for

reading. EF/OR is synchronized to the LOW-to-HIGH transition of CLKB.

ENA

Port A Enable

I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read (from Mail2

register) or write data on Port A.

ENB

Port B Enable

I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write (to

Mail2 register) data on Port B.

FF/IR

Port B Full/Input

Ready Flag

O This is a dual-function pin. In the CY Standard mode, the FF function is selected. FF

indicates whether or not the FIFO memory is full. In the FWFT mode, the IR function is

selected. IR indicates whether or not there is space available for writing to the FIFO

memory. FF/IR is synchronized to the LOW-to-HIGH transition of CLKA.

FS1/SEN

FS0/SD

Flag Offset

Select 1/Serial

Enable

Flag Offset

Select 0/Serial

Data

I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register

programming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select

the flag offset programming method. Three offset register programming methods are

I

available: automatically load one of three preset values (8, 16, or 64), parallel load from

Port A, and serial load. When serial load is selected for flag offset register programming,

FS1/SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA.

When FS1/SEN is LOW, a rising edge on CLKA loads the bit present on FS0/SD into

the X and Y registers. The number of bit writes required to program the offset registers

is 20 for the CY7C43643AV, 24 for the CY7C43663AV, and 28 for the CY7C43683AV.

The first bit Write stores the Y-register MSB and the last bit Write stores the X-register

LSB.

Document #: 38-06024 Rev. *C

Page 4 of 28

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