WED9LC6816V1310BC Ver la hoja de datos (PDF) - White Electronic Designs => Micro Semi

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WED9LC6816V1310BC

256Kx32 SSRAM/4Mx32 SDRAM

White Electronic Designs => Micro Semi 

White Electronic Designs

WED9LC6816V

FIG. 8 SDRAM PAGE READ & WRITE CYCLE AT SAME BANK @

BURST LENGTH = 4

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19

SDCK

SDCE#

tRCD

SDRAS#

SDCAS#

ADDR

Ra

Ca0

Cb0

Note 2

Cc0

Cd0

BA0, 1

[A12,A13]

SDA10

Ra

CL=2

DQ

CL=3

Qa0 Qa1 Qb0 Qb1 Qb2

Qa0 Qa1 Qa2 Qa3

tRDL

Dc0 Dc1 Dd0 Dd1

tCDL

Dc0 Dc1 Dd0 Dd1

SDWE#

BWE#

Row Active

(A-Bank)

Read

(A-Bank)

Read

(A-Bank)

Note 1

Note 3

Write

(A-Bank)

Write

(A-Bank)

Precharge

(A-Bank)

DON’T CARE

NOTES:

1. To write data before burst read ends. BWE# should be asserted three cycle prior to write command to avoid bus contention.

2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge will be written.

3. BWE# should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked

internally.

Contact factory for ordering information.

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

September, 2003

Rev. 1

17

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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