WED9LC6816V1310BC Ver la hoja de datos (PDF) - White Electronic Designs => Micro Semi

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WED9LC6816V1310BC

256Kx32 SSRAM/4Mx32 SDRAM

White Electronic Designs => Micro Semi 

White Electronic Designs

WED9LC6816V

FIG. 7 SDRAM READ & WRITE CYCLE AT SAME BANK @

BURST LENGTH = 4

0

1

2

3

4

5

6

78

9

10 11 12 13 14 15 16 17 18 19

SDCK

SDCE#

Note 1

tRC

tRCD

SDRAS#

SDCAS#

ADDR

Ra

Ca0

Rb

Cb0

BA0, 1

[A12,A13]

SDA10

Ra

CL=2

DQ

CL=3

Rb

tRAC

Note 3 tSAC

tSHZ Note 4

tOH

Qa0 Qa1 Qa2 Qa3

tRAC

Note 3

tSAC

tOH

tSHZ Note 4

Qa0 Qa1 Qa2 Qa3

tRDL

Db0 Db1 Db2 Db3

tRDL

Db0 Db1 Db2 Db3

SDWE#

BWE#

Row Active

(A-Bank)

Read

(A-Bank)

Precharge

(A-Bank)

Row Active

(A-Bank)

Write

(A-Bank)

Precharge

(A-Bank)

DON’T CARE

NOTES:

1. Minimum row cycle times are required to complete internal DRAM operation.

2. Row precharge can interrupt burst on any cycle. (CAS# Latency - 1) number of valid output data is available after Row precharge. Last valid output will be Hi-Z (tSHZ)

after the clock.

3. Access time from Row active command. tCC *(tRCD + CAS# Latency - 1) + tSAC.

4. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)

Contact factory for ordering information.

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

September, 2003

Rev. 1

16

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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