PE3291-11 Ver la hoja de datos (PDF) - Peregrine Semiconductor
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PE3291-11
Peregrine Semiconductor
PE3291-11 Datasheet PDF : 15 Pages
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PE3291
Product Specification
Programmable Divide Values
(R1, R2, F1, F2, A1, A2, M1, M2)
Data is clocked into the 21-bit shift register, MSB
first. When LE is asserted HIGH, data is latched
into the registers addressed by the last two bits
shifted into the 21-bit register, according to Table
7. For example, to program the PLL1 (RF)
swallow counter, A1, the last two bits shifted into
the register (S0, S1) would be (1,1). The 5-bit A1
counter would then be programmed according to
Table 8. For normal operation, S16 of address
(0,0) (the Test bit) must be programmed to 0 even
if PLL2 (IF) is not used.
Table 8. PE3291 Counter Programming Example
Divide Value MSB
LSB Address
S11
S10 S9
S8
S7
S1
S0
A14
A13 A12 A11
A10
1
1
0
0
000
0
11
1
0
000
1
11
2
0
001
0
11
-
-
-
-
-
-
11
31
1
111
1
11
Program Modes
Several modes of operation can be programmed with bits C10 - C14 and C20 - C24, including the phase detector
polarity, charge pump high impedance, output of the foLD pin and power-down modes. The PE3291 modes of
operation are shown on Table 9. The truth table for the foLD output is shown in Table 10.
Table 9. PE3291 Program Modes
S15
S14
S13
S12
S11
S1
S0
C24
See Table 10
C23
See Table 10
C22
0 = PLL2 CP normal
C21 (Note 2)
0 = PLL2 Phase Detector inverted
C20 (Note 1)
0 = PLL2 on
0
0
C14
See Table 10
C13
See Table 10
1 = PLL2 CP High Z
C12
0 = PLL1 CP normal
1 = PLL2 Phase Detector normal
C11 (Note 2)
0 = PLL1 Phase Detector inverted
1 = PLL2 off
C10 (Note 1)
0 = PLL1 on
1
0
1 = PLL1 CP High Z 1 = PLL1 Phase Detector normal 1 = PLL1 off
Note 1:
Note 2:
The PLL1 power-down mode disables all of PLL1’s components except the R1 counter and the reference frequency input buffer, with
CP1 (pin 3) and fin1 (pin 5) becoming high impedance. The power down of PLL2 has similar results with CP2 (pin 18) and fin2 (pin 16)
becoming high impedance. Power down of both PLL1 and PLL2 further disables counters R1 and R2, the reference frequency input, and
the foLD output, causing fr (pin 8) and foLD (pin 10) to become high impedance. The Serial Control Interface remains active at all times.
The C11 and C21 bits should be set according to the voltage versus frequency slope of the VCO as shown in Figure 9. This relationship
presumes the use of a passive loop filter. If an inverting active loop filter is used the relationship is also inverted.
Figure 9. VCO Characteristics
VCO
Output
Frequency
(1) Positive slope VCO
(2) Negative slope VCO
VCO Input voltage
• When VCO1 (RF) slope is positive like (1), C11 should be set HIGH.
• When VCO1 (RF) slope is negative like (2), C11 should be set LOW.
• When VCO2 (IF) slope is positive like (1), C21 should be set HIGH.
• When VCO2 (IF) slope is negative like (2), C21 should be set LOW.
Document No. 70-0009-04 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
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