3291-00 Ver la hoja de datos (PDF) - Peregrine Semiconductor
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componentes Descripción
Fabricante
3291-00
Peregrine Semiconductor
3291-00 Datasheet PDF : 15 Pages
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PE3291
Product Specification
Functional Description
The Functional Block Diagram in Figure 7 shows a
21-bit serial control register, a multiplexed output,
and PLL sections PLL1 and PLL2. Each PLL
contains a fractional-N main counter chain, a
reference counter, a phase detector, and an
internal charge pump with on-chip fractional spur
compensation. Each fractional-N main counter
chain includes an internal dual modulus prescaler,
supporting counters, and a fractional accumulator.
Serial input data is clocked on the rising edge of
Clock, MSB first. The last two bits are the address
bits that determine the register address. Data is
transferred into the counters as shown in Table 8,
PE3291 Register Set. If the foLD pin is configured
as data out, then the contents of shift register bit
S20 are clocked on the falling edge of Clock onto
the foLD pin. This feature allows the PE3291 and
compatible devices to be connected in a daisy-
chain configuration.
The PLL1 (RF) VCO frequency fin1 is related to
Figure 7. Functional Block Diagram
the reference frequency fr by the following
equation:
fin1 = [(32 x M1) + A1 + (F1/32)] x (fr/R1)
(1) Note that A1 must be less than M1. Also, fin1
must be greater than or equal to 1024 x (fr/R1) to
obtain contiguous channels.
The PLL2 (IF) VCO frequency fin2 is related to the
reference frequency fr by the following equation:
fin2 = [(16 x M2) + A2 + (F2/32)] x (fr/R2)
(2) Note that A2 must be less than M2. Also, fin2
must be greater than or equal to 256 x (fr/R2) to
obtain contiguous channels.
F1 sets PLL1 fractionality. If F1 is an even number,
the PE3291 automatically reduces the fraction.
For example, if F1 = 12, then the fraction 12/32 is
automatically reduced to 3/8. In this way,
fractional denominators of 2, 4, 8, 16 and 32 are
available. F2 sets the fractionality for PLL2 in the
same manner.
fin1
fr
Clock
Data
LE
P1
P2
32/33
Prescaler
A1
5
A1 Counter
0<A1<31
M1
9
M1 Counter
3<M1<511
Ref.
Amp.
9-bit Reference
Divider
R1
9
21-bit Serial Control
Interface
R2
9
9-bit Reference
Divider
Prescaler
Control Logic
F1
5
F1 Counter
0<F1<31
Fractional Spur
Compensation
Phase
Detector
Charge
Pump
C11
C12
C22
Multiplexer
C22
C22
C22
C21
C22
Phase
Detector
Charge
Pump
CP1
foLD
CP2
fin2
16/17
Prescaler
P1
P2
Document No. 70-0009-04 │ www.psemi.com
M2 Counter
3<M2<511
M2
9
A2 Counter
0<A2<15
A2
4
F2 Counter
0<F2<31
F2
5
Prescaler
Control Logic
Fractional Spur
Compensation
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 15
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