3291-00 Ver la hoja de datos (PDF) - Peregrine Semiconductor
Número de pieza
componentes Descripción
Fabricante
3291-00
Peregrine Semiconductor
3291-00 Datasheet PDF : 15 Pages
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PE3291
Product Specification
Table 2. Absolute Maximum Ratings
Symbol Parameter/Conditions Min Max Units
VDD
Supply voltage
VI
Voltage on any input
II
DC into any input
IO
DC into any output
Tstg
Storage temperature
range
-0.3 4.0
V
-0.3 VDD
V
+ 0.3
-10 +10 mA
-10 +10 mA
-65 150 °C
Absolute Maximum Ratings are those values listed in
the above table. Exceeding these values may cause
permanent device damage. Functional operation
should be restricted to the limits in the DC and AC
Characteristics table. Exposure to absolute maximum
ratings for extended periods may affect device
reliability.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 3. Operating Ratings
Symbol
VDD
TA
Parameter/Conditions
Supply voltage
Operating ambient
Min Max Units
2.7 3.3
V
-40 85
°C
Table 4. ESD Ratings
Symbol
Parameter/Conditions
VESD
ESD voltage human body model
Level Units
1000
V
Note 1: Periodically sampled, not 100% tested. Tested per MIL-
STD-883, M3015 C2
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
specified rating in Table 4.
Table 5. DC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
IDD
3 V supply current when VDD1 (10 MHz Ref. Freq.)
and VDD2 are internally
P2, P1 = 01 RF
RF PLL1 low speed
1.4
regulated down from VDD
(note 1)
P2, P1 = 1X
RF PLL1 high speed
2.0
C10, C20 = 01
IF PLL2 off
P2, P1 = 01
RF PLL1 low speed
2.1
C10, C20 = 00
IF PLL2 low speed
P2, P1 = 10
RF PLL1 high speed
2.7
C10, C20 = 00
IF PLL2 low speed
P2, P1 = 11
RF PLL1 high speed
3.1
C10, C20 = 00
IF PLL2 high speed
IDD
3 V supply current when VDD1 P2, P1 = 00
2 PLL’s enabled
1.0
and VDD2 are externally
1 PLL enabled
0.7
supplied (note 1)
Max
Units
mA
mA
mA
mA
mA
mA
mA
IDD1
PLL1 FlexiPower Prescaler
P2, P1 = 00
PLL1 enabled
supply current (see fig. 5)
VDD1 = 1/0 volt
VDD1 = 1.8 volts
VDD1 = 2.7 volts
0.5
mA
1.5
mA
4.0
mA
IDD2
PLL2 FlexiPower Prescaler
supply current (see fig. 5)
Istby
Total standby current
Digital inputs: Clock, Data, LE
VIH
High level input voltage
VIL
Low level input voltage
IIH
High level input current
IIL
Low level input current
P2, P1 = 00
VDD2 = 1.0 volt
VDD2 = 1.8 volts
VDD2 = 2.7 volts
PLL2 enabled
VDD = 2.7 to 3.3 volts
VDD = 2.7 to 3.3 volts
VIH = VDD = 3.3 volts
VIL = 0, VDD = 3.3 volts
0.4
mA
1.2
mA
2.0
mA
5
50
mA
0.7 x VDD
-1
-1
V
0.3 x VDD
V
+1
mA
+1
mA
Note 1: The total current consumed by the device is IDD when internal regulation is employed and IDD + IDD1 + IDD2 when VDD1 and VDD2 are
externally supplied. When VDD1 and VDD2 are internally generated, pins 7 and 14 should be left floating.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 15
Document No. 70-0009-04 │ UltraCMOS™ RFIC Solutions
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