YGV627-V(2005) Ver la hoja de datos (PDF) - Yamaha Corporation
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YGV627-V Datasheet PDF : 24 Pages
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YGV627
λ WAIT ( O: PULL UP, 3-state output )
This is data wait signal output to CPU. When CSREG or CSMEM is active, the level of WAIT signal is
made low once with respect to RD or WR1, WR0 in accordance with the internal state of YGV627, and in
accessible state, it outputs high level.
When CSREG or CSMEM is not active, it is in high impedance state, and when CSREG or CSMEM is
active and RD or WR1, WR0 is not active, high level is outputted from this pin.
Some CPU must use READY signal instead of this signal.
A22-A1
CSREG, CSMEM
A0/WR1, W¯¯R¯¯0
D15-0 (input)
¯W¯A¯¯IT¯
Hi-Z
VALID
VALID
Hi-Z
WAIT signal at write access
λ INT ( O: Open drain output )
This is interrupt request signal output to CPU.
This signal is made low when the internal state of YGV627 coincides with the setting conditions of registers.
This signal is reset with access to YGV627’s internal register.
λ INT2 ( O: High speed bus interrupt output )
This is an interrupt request signal output to CPU, and its output logical value is the same as that of INT.
For high speed CPU bus, this output signal is used to avoid the influence of transit time caused by the pull-up
resistor when the interrupt signal is negated.
Use INT or INT2 in accordance with the requirement of the system into which the YGV627 is built-in.
λ LWD ( I: PULL UP )
This is used to select width of CPU data bus.
When this signal is high level input, the device is compatible with 16 bit system and when low level input, the
device is compatible with 8 bit system respectively.
Since LWD is used for selection of a mode, always fix it to either level.
λ RESET ( I: PULL UP, with Schmitt )
Initial reset signal is inputted to RESET. The reset signal input resets the internal state of the device and the
internal registers are cleared to “0”. (Some registers are loaded with initial value.)
Be sure to input the reset signal after power up.
λ DREQ ( O )
DREQ outputs command data request signal to external DMA controller.
λ DACK ( I: PULL UP )
Command data transfer permission signal is inputted to DACK in response to DREQ signal to external DMA
controller.
λ DMAP ( I: PULL UP )
DMAP is used to select a register space mapping method.
When high level is inputted, 16 byte indirect mapping is selected. When low level is inputted, all the registers
except CLUT are mapped directly in the 128 byte space. The input to DMAP determines the valid address when
CSREG signal is active.
DMAP input signal is valid regardless of the state of ENH input signal.
When using YGV627 in YGV617B compatibility mode, input high level to DMAP.
Since DMAP is for selection of a mode, always fix it to either level.
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