MU9C3640L-90TZC Ver la hoja de datos (PDF) - Music Semiconductors
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MU9C3640L-90TZC Datasheet PDF : 20 Pages
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OPERATIONAL CHARACTERISTICS Continued
LIST-XL
most-significant portion of each entry. The CAM/RAM
partitioning is allowed on 16-bit boundaries, permitting
selection of the configuration shown in Table 7 on page 15,
bits 8–6 (e.g., “001” sets the 48 MSBs to CAM and the 16
LSBs to RAM). Memory Array bits designated as RAM
can be used to store and retrieve data associated with the
CAM content at the same memory location.
Memory Access
There are two general ways to get data into and out of the
memory array: directly or by moving the data through the
Comparand or mask registers.
The first way, through direct reads or writes, is set up by
issuing a Set Persistent Destination (SPD) or Set Persistent
Source (SPS) command. The addresses for the direct access
can be directly supplied; supplied from the Address register,
supplied from the Next Free Address register, or supplied as
the Highest-Priority Match address. Additionally, all the direct
writes can be masked by either mask register.
The second way is to move data via the Comparand or
mask registers. This is accomplished by issuing Data Move
commands (MOV). Moves using the Comparand register
can also be masked by either of the mask registers.
The minimum timings for the /E control signal are given in
the Switching Characteristics section on page 18. Note that
at minimum timings the /E signal is non-symmetrical, and
that different cycle types have different timing requirements,
as given in Table 6 on page 15.
COMPARE OPERATIONS
During a Compare operation, the data in the Comparand
register is compared to all locations in the Memory array
simultaneously. Any mask register used during compares
must be selected beforehand in the Control register. There
are two ways compares are initiated: Automatic and Forced
compares.
Automatic compares perform a compare of the contents of the
Comparand register against Memory locations that are tagged
as “Valid,” and occur whenever the following happens:
q The Destination Segment counter in the Segment
Control register reaches its end limit during writes to
the Comparand or mask registers.
q After a command write of a TCO CT is executed (except
for a software reset), so that a compare is executed
with the new settings of the Control register.
I/O CYCLES
The LIST-XL supports four basic I/O cycles: Data Read, Data
Write, Command Read, and Command Write. The type of cycle
is determined by the states of the /W and /CM control inputs.
These signals are registered at the beginning of a cycle by the
falling edge of /E. Table 2 on page 2 shows how the /W and
/CM lines select the cycle type.
Forced compares are initiated by CMP instructions
using one of the four validity conditions, V, R, S, and E.
The forced compare against “Empty” locations
automatically masks all 64 bits of data to find all locations
with the validity bits set to “Empty,” while the other
forced compares are masked only as selected in the
Control register.
During Read cycles, the DQ15–0 outputs are enabled after
/E goes LOW. During Write cycles, the data or command
to be written is captured from DQ15–0 at the beginning of
the cycle by the falling edge of /E. Figures 1 and 2 on page
10 show Read and Write cycles respectively. Figure 3 on
page 10 shows typical cycle-to-cycle timing with the Match
flag valid at the end of the Comparand Write cycle. Data
writes and reads to the comparand, mask registers, or
memory occur in one to four 16-bit cycles, depending on
the settings in the Segment Control register. The Compare
operation automatically occurs during Data writes to the
Comparand or mask registers when the destination segment
counter reaches the end count set in the Segment Control
register. If there was a match, the second cycle reads status
or associated data, depending on the state of /CM.
INITIALIZING THE LIST-XL
Initialization of the LIST-XL is required to configure the
various registers on the device. Since a Control register
reset establishes the operating conditions shown in Table
4 on page 8, restoration of operating conditions better suited
for the application may be required after a reset, whether
using the Control Register reset or the /RESET pin. When
the device powers up, the memory and registers are in an
unknown state, so the /RESET pin must be asserted to
place the device in a known state.
9
Rev. 2
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