AS7C34096-20JC Ver la hoja de datos (PDF) - Alliance Semiconductor

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componentes Descripción

Fabricante

AS7C34096-20JC

5V/3.3V 512K × 8 CMOS SRAM

Alliance Semiconductor 

AS7C4096

AS7C34096

®

Write cycle (over the operating range)11

–10

Parameter

Symbol Min Max

Write cycle time

tWC 10

–

Chip enable (CE) to write end

tCW

7

–

Address setup to write end

tAW

7

–

Address setup time

tAS

0

–

Write pulse width (OE = high) tWP1 7

–

Write pulse width (OE = low

tWP2 10

–

Address hold from end of write tAH

0

–

Write recovery time

tWR

0

–

Data valid to write end

tDW

5

–

Data hold time

tDH

0

–

Write enable to output in high Z tWZ 0

5

Output active from write end

tOW

3

–

–12

Min Max

12

–

8

–

8

–

0

–

8

–

12

–

0

–

0

–

6

–

0

–

0

6

3

–

–15

Min Max

15

–

10

–

10

–

0

–

10

–

15

–

0

–

0

–

7

–

0

–

0

7

3

–

–20

Min Max

20

–

12

–

12

–

0

–

12

–

20

–

0

–

0

–

9

–

0

–

0

9

3

–

Unit Notes

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns 4, 5

ns 4, 5

ns 4, 5

Write waveform 1 (WE controlled)10,11

tWC

Address

WE

DIN

DOUT

tAW

tWP

tAS

tWZ

tWR

tAH

tDW

Data valid

tDH

tOW

Write waveform 2 (CE controlled)10,11

Address

CE

WE

DIN

tWC

tAW

tAS

tCW

tWP

tWZ

DOUT

tWR

tAH

tDW

tDH

Data valid

1/13/05; v.1.9

Alliance Semiconductor

P. 5 of 9

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