AS4LC1M16S1-10TC Ver la hoja de datos (PDF) - Alliance Semiconductor
Número de pieza
componentes Descripción
Fabricante
AS4LC1M16S1-10TC Datasheet PDF : 28 Pages
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AS4LC2M8S1
AS4LC1M16S1
Operating modes
Command
CKEn-1 CKEn CS
Mode register set
H
X
L
Auto refresh
H
H
L
Self
refresh
Entry
Exit
H
L
L
L
L
H
H
Bank activate
H
X
L
Auto precharge disable
Read
H
X
L
Auto precharge enable
Auto precharge disable
Write
H
X
L
Auto precharge enable
Burst stop
H
X
L
Selected bank
Precharge
Both banks
H
X
L
Clock suspend or
active power down
Entry
Exit
H
H
L
L
L
HX
Precharge power
down mode
Entry
Exit
H
H
L
L
H
L
H
L
DQM
H
X
X
No operation command
H
H
X
L
RAS CAS
L
L
L
L
L
L
HH
XX
LH
HL
HL
HH
LH
XX
VV
XX
XX
HH
XX
HH
XX
XX
HH
WE DQM A11 A10 A9–A0 Note
LX
Op code
1,2
HX
X
3
HX
X
3
HX
X
3
XX
X
3
H
X
V* row address
H
X
V
L column 4
H address 4,5
L
X
V
L column 4
H address 4,5
LX
X
6
VL
LX
X
XH
XX
VX
X
XX
XX
HX
X
XX
HX
XVXX
X
7
XX
X
HX
* V = Valid.
1 OP= operation code.
A0~A11 see page 5.
2 MRS can be issued only when both banks are precharged and no data burst is ongoing. A new command can be issued 2 clock cycles a fter MRS.
3 Auto refresh functions similarly to CBR DRAM refresh. However, precharge is automatic.
Auto/self refresh can only be issued after both banks are precharged.
4 A11: bank select address. If low during read, write, row active and precharge, bank A is selected.
If high during those states, bank B is selected. Both banks are selected and A11 is ignored if A10 is high during row precharge.
5 A new read/write/deac command to the same bank cannot be issued during a burst read/write with auto precharge.
A new row active command can be issued after t RP from the end of the burst.
6 Burst stop command valid at every burst length except full-page burst.
7 DQM sampled at positive edge of CLK. Data-in may be masked at every CLK (Write DQM latency is 0).
Data-out mask is active 2 CLK cycles after issuance. (Read DQM latency is 2).
4
ALLIANCE SEMICONDUCTOR
7/5/00
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