AS4LC1M16S1(2000) Ver la hoja de datos (PDF) - Alliance Semiconductor
Número de pieza
componentes Descripción
Fabricante
AS4LC1M16S1 Datasheet PDF : 28 Pages
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AS4LC2M8S1
AS4LC1M16S1
Pin descriptions
Pin
CLK
CKE
CS
A0~A10
A11
RAS
CAS
WE
×8: DQM
×16: UDQM, LDQM
DQ0~DQ15
VCC/VSS
VCCQ/VSSQ
Name
System clock
Clock enable
Chip select
Address
Bank select
Row address strobe
Column address strobe
Write enable
Output disable/ write mask
Data input/output
Power supply/ground
Data output power/ground
Description
All operations synchronized to rising edge of CLK.
Controls CLK input. If CKE is high, the next CLK rising edge is valid.
If CKE is low, the internal clock is suspended from the next clock
cycle and the burst address and output states are frozen. If both banks
are idle and CKE goes low, the SDRAM will enter power down mode
from the next clock cycle. When in power down mode and CKE is
low, no input commands will be acknowledged. To exit power down
mode, raise CKE high before the rising edge of CLK.
Enables or disables device operation by masking or enabling all
inputs except CLK, CKE, UDQM/LDQM (×16), DQM (×8).
Row and column addresses are multiplexed. Row address: A0~A10.
Column address (2M × 8): A0~A8. Column address (1M × 16):
A0~A7.
Memory cell array is organized in 2 banks. A11 selects which internal
bank will be active. A11 is latched during bank activate, read, write,
mode register set, and precharge operations. Asserting A11 low
selects Bank A; A11 high selects Bank B.
Command inputs.
RAS, CAS, and WE, along with CS, define the command being
entered.
Controls I/O buffers. When DQM is high, output buffers are disabled
during a read operation and input data is masked during a write
operation. DQM latency is 2 clocks for Read and 0 clocks for Write.
For ×16, LDQM controls the lower byte (DQ0 – 7) and UDQM
controls the upper byte (DQ8 – 15). UDQM and LDQM are
considered to be in the same state when referred to jointly as DQM.
Data inputs/outputs are multiplexed.
Power and ground for core logic and input buffers.
Power and ground for data output buffers.
7/5/00
ALLIANCE SEMICONDUCTOR
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