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SAA7212H

Integrated MPEG AVG decoder

Philips Electronics 

Philips Semiconductors

Integrated MPEG AVG decoder

Preliminary specification

SAA7212

FEATURES

General features

• Single external Synchronous DRAM organized

as 1 M × 16 interfacing at 81 MHz. Due to efficient

memory use in MPEG decoding, more than 1 Mbit

available for graphics

• Fast 16-bit data + 8-bit address interface with external

controller on 27 MHz. Sustained data rate to external

SDRAM ≤9 Mbytes/s in bursts of 128 bytes

• Dedicated input for audio and video in PES or ES in byte

wide. Data input rate: ≤9 Mbytes/s in byte mode.

Accompanying strobe signals distinguish between audio

and video data

• Dedicated compressed data input compatible with the

VLSI VES2020/2030 demultiplexers; video is received

in byte format and audio serially

• Audio and/or video can also be input via the CPU

interface in PES/ES in 8 or 16-bit parallel format up to a

peak data rate of 9 Mbytes/s

• Single 27 MHz external clock for time base reference

and internal processing. Internal system time base at

90 kHz can be synchronized via CPU port. All required

decoding and presentation clocks are generated

internally

• Flexible memory allocation under control of the external

CPU enables optimized partitioning of memory for

different tasks

• Boundary scan testing implemented

• External SDRAM self test

• Supply voltage 3.3 V

• Package QFP160.

CPU related features

• 16 bits data, 8 bits address, or 16 bits multiplexed bus.

Motorola 68xxx and Intel x 86 compatible.

• Support fast DMA transfer

• Flexible bidirectional interface to external SDRAM.

Minimum sustained rate is 9 Mbytes/s

• Enhanced block mover allows 3 D data move in the

external SDRAM. Picture move/Graphic bit maps

construction can be done with minimum CPU support.

MPEG2 system features

• Parsing of MPEG2 PES and MPEG1 packet streams

• Double system time clock counters

• Stand-alone or supervised audio/video synchronization

• Processing of errors flagged by channel decoding

section

• Support for retrieval of PES header.

MPEG2 video features

• Decoding of MPEG2 video up to main level, main profile

• Output picture format: CCIR-601 4 : 2 : 2 interlaced

pictures. Picture format 720 × 576 at 50 Hz or 720 × 480

at 60 Hz

• Support of constant and variable bit rates up to

15 Mbits/s

• Stand-alone or CPU controlled mode for

decoding/display processes

• Stand-alone mode can be used by applications requiring

still pictures manipulations

• Output interface at 8-bit wide, 27 MHz UYVY

multiplexed bus

• Horizontal and vertical pan and scan allows the

extraction of a window from the coded picture

• Flexible horizontal scaling from 0.5 up to 4 allows easy

aspect ratio conversion including support

for 2.21 : 1 aspect ratio movies. In case of shrinking an

anti-aliasing pre-filter is applied

• Vertical scaling with fixed factors 0.5, 1 or 2. Factor 0.5,

realizing picture shrink. Factor 2 can be used for

up-conversion of pictures with 288 (240) lines or less.

• Vertical down-scaling with 0.75 factor, realizing letter

box conversion

• Horizontal and vertical scaling can be combined to scale

pictures to 1⁄4 their original size, thus freeing up screen

space for graphic applications like electronic program

guides

• Non full screen MPEG pictures will be displayed in a box

of which position and background colour are adjustable

by the external microcontroller

• Nominal video input buffer size for ml@mp 2.7 Mbit

• Video output may be slaved to internally (master)

generated or externally (slave) supplied HV

synchronization signals. The position of active video is

programmable. Display phase is not affected by MPEG

timebase changes.

1998 Sep 07

2

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