BR93LC46FJ-W Ver la hoja de datos (PDF) - ROHM Semiconductor
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BR93LC46FJ-W Datasheet PDF : 11 Pages
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Memory ICs
BR93LC46-W / BR93LC46F-W / BR93LC46RF-W /
BR93LC46FJ-W / BR93LC46RFJ-W / BR93LC46FV-W
(7) All address write (Fig.13)
With this command, the input 16 bits data is written simultaneously to all of the addresses (64 words). Rather than
writing one word at a time, in succession, data is written all at one time, enabling a write time of tE / W.
tSV
CS
STATUS
1
2
5
10
25
SK
DI
1
0
0
0
1
D15 D14
D1 D0
DO
High Z
Fig.13 Write all address cycle timing. (WRAL)
tCS
BUSY READY
tE / W
(8) Write disable (Fig.14)
When the power supply is turned on, the IC enters the write disable status. Similarly, when the write disable command
is issued, the IC enters the same status. When in this status, all write commands are ignored, but read commands
may be executed.
In the write enable status, writing begins even if a write command is entered accidentally. To prevent errors of this type,
we recommend executing a write disable command after writing has been completed.
CS
SK
DI
1
0
0
0
0
DO
High Z
Fig.14 Write disable cycle timing (WDS)
zOperation notes
(1) Cancelling modes
〈READ〉
Start bit
1 bit
Operating code
2 bits
Address
6 bits
Data
16 bits
Cancel can be performed for the entire read mode space
Cancellation method: CS LOW
〈WRITE, WRAL〉
Start bit
1 bit
Operating code
2 bits
Address
6 bits
Data
16 bits
tE / W
a
b
∗ a: Canceled by setting CS LOW or VCC OFF ( )
b: Cannot be canceled by any method. If VCC is set to OFF during this time, the data in the
designated address is not secured.
∗ VCC OFF (VCC is turned off after CS is set to LOW)
Fig.15
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