BR93A76-WM Ver la hoja de datos (PDF) - ROHM Semiconductor
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BR93A76-WM Datasheet PDF : 41 Pages
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BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
Technical Note
●Action timing characteristics
(BR93L□□-W, Ta=-40～+85℃, VCC=2.5～5.5V, BR93A□□-WM, Ta=-40～+105℃, VCC=2.5～5.5V)
Parameter
Symbol
2.5V≦VCC≦5.5V
Min.
Typ.
Max.
Unit
SK frequency
fSK
-
-
2
MHz
SK “H” time
SK “L” time
tSKH
230
-
-
ns
tSKL
230
-
-
ns
CS “L” time
tCS
200
-
-
ns
CS setup time
DI setup time
tCSS
50
-
-
ns
tDIS
100
-
-
ns
CS hold time
tCSH
0
-
-
ns
DI hold time
Data “1” output delay time
tDIH
100
-
-
ns
tPD1
-
-
200
ns
Data “0” output delay time
tPD0
-
-
200
ns
Time from CS to output establishment
Time from CS to High-Z
tSV
-
-
150
ns
tDF
-
-
150
ns
Write cycle time
tE/W
-
-
5
ms
(BR93L□□-W, Ta=-40～+85℃, VCC=1.8～2.5V)
Parameter
Symbol
1.8V≦VCC≦2.5V
Min.
Typ.
Max.
Unit
SK frequency
fSK
-
-
500
kHz
SK “H” time
tSKH
0.8
-
-
us
SK “L” time
tSKL
0.8
-
-
us
CS “L” time
tCS
1
-
-
us
CS setup time
tCSS
200
-
-
ns
DI setup time
tDIS
100
-
-
ns
CS hold time
tCSH
0
-
-
ns
DI hold time
tDIH
100
-
-
ns
Data “1” output delay time
tPD1
-
-
0.7
us
Data “0” output delay time
tPD0
-
-
0.7
us
Time from CS to output establishment
tSV
-
-
0.7
us
Time from CS to High-Z
tDF
-
-
200
ns
Write cycle time
tE/W
-
-
5
ms
●Sync data input / output timing
CS
tCSS
tSK H
tS KL
SK
t DIS
tDI H
DI
t PD0
tPD1
DO(READ)
DO(WRITE)
STATUS VALID
tCS H
tDF
Fig.1 Sync data input / output timing
○Data is taken by DI sync with the rise of SK.
○At read action, data is output from DO in sync with the rise of SK.
○The status signal at write (READY / BUSY) is output after tCS from the fall of CS after write command input, at the area
DO where CS is “H”, and valid until the next command start bit is input. And, while CS is “L”, DO becomes High-Z.
○After completion of each mode execution, set CS “L” once for internal circuit reset, and execute the following action mode.
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2011.02 - Rev.F
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