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BR34E02NUX-3

Memory for Plug & Play DDR2/DDR3 SPD Memory (for Memory Modules)

ROHM Semiconductor 

BR34E02FVT-3,BR34E02NUX-3

Technical Note

●Data transfer on the I2C BUS

○Data transfer on the I2C BUS

The BUS is considered to be busy after the START condition and free a certain time after the STOP condition.

Every SDA byte must be 8-bits long and requires an ACKNOWLEDGE signal after each byte. The devices have Master

and Slave configurations. The Master device initiates and ends data transfer on the BUS and generates the clock signals

in order to permit transfer.

The EEPROM in a slave configuration is controlled by a unique address. Devices transmitting data are referred to as the

Transmitter. The devices receiving the data are called Receiver.

○START Condition (Recognition of the START bit)

・All commands are proceeded by the start condition, which is a High to Low transition of SDA when SCL is High.

・The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command

until this condition has been met. (See Fig.1-(b) START/STOP Bit Timing)

○STOP Condition (Recognition of STOP bit)

・All communications must be terminated by a stop condition, which is a Low to High transition of SDA when SCL is High.

(See Fig.1-(b) START/STOP Bit Timing)

○Write Protect By Soft Ware

・Set Write Protect command and permanent set Write Protect command set data of 00h～7Fh in 256 words write

protection block. Clear Write Protect command can cancel write protection block which is set by set write Protect

command. Cancel of write protection block which is set by permanent set Write Protect command at once is

impossibility. When these commands are carried out, WP pin must be OPEN or GND.

○Acknowledge

・ Acknowledge is a software used to indicate successful data transfers. The Transmitter device will release the BUS after

transmitting eight bits. When inputting the slave address during write or read operation, the Transmitter is the µ-COM.

When outputting the data during read operation, the Transmitter is the EEPROM.

・During the ninth clock cycle the Receiver will pull the SDA line Low to verify that the eight bits of data have been

received. (When inputting the slave address during write or read operation, EEPROM is the receiver. When outputting

the data during read operation the receiver is the µ-COM.)

・The device will respond with an Acknowledge after recognition of a START condition and its slave address (8bit).

・In WRITE mode, the device will respond with an Acknowledge after the receipt of each subsequent 8-bit word (word

address and write data).

・In READ mode, the device will transmit eight bits of data, release the SDA line, and monitor the line for an Acknowledge.

・If an Acknowledge is detected and no STOP condition is generated by the Master, the device will continue to transmit

the data. If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP

condition before returning to standby mode.

○Device Addressing

・Following a START condition, the Master outputs the Slave address to be accessed. The most significant four bits

of the slave address are the “device type indentifier.” For this EEPROM it is “1010.” (For WP register access this code

is "0110".)

・The next three bits identify the specified device on the BUS (device address). The device address is defined by the state

of the A0,A1 and A2 input pins. This IC works only when the device address input from the SDA pin corresponds to the

status of the A0,A1 and A2 input pins. Using this address scheme allows up to eight devices to be connected to the

BUS.

・The last bit of the stream (R/W…READ/WRITE) determines the operation to be performed.

R/W=0 ････ WRITE (including word address input of Random Read)

R/W=1 ････ READ

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© 2011 ROHM Co., Ltd. All rights reserved.

7/19

2011.11 - Rev.A

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