BR24C21FV Ver la hoja de datos (PDF) - ROHM Semiconductor

Número de pieza

componentes Descripción

Fabricante

BR24C21FV

EDID Memory (For display)

ROHM Semiconductor 

BR24C21xxx Series (1K)

Datasheet

●Bi-directional mode

○Bi-directional Mode and Recovery Function

・The BR24C21/F/FJ/FV can be switched from Transmit-Only Mode to Bi-directional Mode by providing a valid High to Low

transition at the SCL pin, while the state of SDA is at high-impedance.

・After a valid high to low transition on the SCL pin, the BR24C21/F/FJ/FV begins to count the VCLK clock. If the VCLK

counter reaches 128 clocks without the command for Bi-directional Mode, the device reverts to Transmit-Only Mode

(Recovery function). The VCLK counter is reset by providing a valid high to low transition at the SCL pin. After reversal to

Transmit-Only Mode the device begins to output data (00h address data) with the 129th rising clock edge of VCLK.

・If the BR24C21/F/FJ/FV is switched from Transmit-Only Mode and receives the command for Bi-directional

Mode and responds with an Acknowledge, it is impossible to revert to Transmit-Only Mode. (Power down is the only

way to revert to Transmit-Only Mode.) Unless the input device code is “1010”, the device does not respond with an

Acknowledge. If the VCLK counter reaches 128 clocks afterwards, it is possible to revert to Transmit-Only Mode for

Recovery function. If the Master generates a STOP condition during the Slave address, before an Acknowledge is input,

it is possible to revert to Transmit-Only Mode.

・When the device is switched from Transmit-Only Mode to Bi-direction Mode, the period of tVHZ needs to be held.

Transmit-only

ＭＯＤＥ Transmit-only

B i - dBii-rdeircecttiioonnaal l

T r aTnrasnistiitioonn MModeo dwieth wpoistshibipliotys stoi b i l i t y

t o rreettuurnnteo TtroansTmirta-OnnslymMiotd-eO n l y M o d e

Transmit-Only

Transmit-Only

ＶＣＬＫ

１２３４

１２７ １２８ １２９

Transmit-only

Transmit-oOnly

ＭＯＤＥ

BBii--ddirierceticontailo n a l

TTrraansnitsiiotni oMonde Mwiothdpeosswibiitlhityptoos s i b i l i t y

troeturren ttuo nTreanstmoit-TOrnlaynMsodme i t - O n l y M o d e

ＶＣＬＫ

１２

ｎ＜１２８

ｎ

B i - d i rBie-cditrieoctnioanal l

p a r m paanrmeannent tl lyy

ＳＣＬ

ＳＤＡ

ｔＶＨＺ

A D DADRDREESSSS000h0 h

Ｄ７ Ｄ６ Ｄ５ Ｄ４

ＳＣＬ

ＳＤＡ

ｔＶＨＺ

Ｓ １ ０ １ ０ ＊ ＊ ＊ Ｒ/Ｗ ＡＣＫ

*Don’t care

Figure 6. Recovery Mode

Figure 7. Mode Change

○Bi-directional Mode

START Condition

・All commands are proceeded by the START condition, which is a High to Low transition of SDA when SCL is High.

・The BR24C21/F/FJ/FV continuously monitors the SDA and SCL lines for the START condition and will not respond to

any commands until this condition has been met.

(See Figure 1 Synchronous Data Timing)

STOP Condition

・All commands must be terminated by a STOP condition, which is a Low to High transition of SDA when SCL is High.

・The STOP condition causes the internal write cycle to write data into the memory array after a write sequence.

・The STOP condition is also used to place the device into standby power mode after read sequences.

・A STOP condition can only be issued after the transmitting device has released the bus.

(See Figure 1 Synchronous Data Timing)

Device Addressing

・Following the START condition, the Master outputs the device address of the Slave to be accessed. The most significant

four bits of Slave address are the “device type indentifier,” For the BR24C21/F/FJ/FV this is fixed as “1010.”

・The next three bits of the slave address are inconsequential.

・The last bit of the stream determines the operation to be performed. When set to “1”, a READ operation is selected.

When set to “0”, a WRITE operation is initiated.

R/W set to "0" ・ ・ ・ ・ ・ ・ ・ ・ WRITE (This bit is also set to "0" for random read operation)

R/W set to "1" ・ ・ ・ ・ ・ ・ ・ ・ READ

1010

_

＊

＊

＊

R/W

＊：Don’t care

○Write Protect Function

・Write Enable (VCLK)

When using the BR24C21/F/FJ/FV in Bi-directional Mode, the VCLK pin can be used as a write enable pin. Setting VCLK

High allows normal write operations, while setting VCLK low prevents writing to any location in the array.

(See Figure 3 Write Enable Timing)

Changing VCLK from High to Low during the self-timed program operation will not halt programming of the device.

www.rohm.com

© 2012 ROHM Co., Ltd. All rights reserved.

TSZ22111・15・001

5/18

TSZ02201-0R2R0G100270-1-2

10.Jul.2012 Rev.001

Share Link: