BF1212WR Ver la hoja de datos (PDF) - NXP Semiconductors.
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BF1212WR Datasheet PDF : 16 Pages
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NXP Semiconductors
N-channel dual-gate MOS-FETs
Product specification
BF1212; BF1212R; BF1212WR
30
handbook, halfpage
IG1
(μA)
20
10
MLE241
(1)
(2)
(3)
(4)
(5)
0
handbook, halfpage
gain
reduction
(dB)
−20
−40
MLE242
0
0
2
4
6
VG2-S (V)
(1) VGG = 5 V.
(2) VGG = 4.5 V.
(3) VGG = 4 V.
(4) VGG = 3.5 V.
(5) VGG = 3 V.
VDS = 5 V; Tj = 25 C.
RG1 = 150 k
(connected to VGG);
see Fig.21.
Fig.13 Gate 1 current as a function of gate 2
voltage; typical values.
−60
0
1
2
3
4
VAGC (V)
VDS = 5 V; VGG = 5 V; RG1 = 150 k(connected to VGG);
see Fig.21; f = 50 MHz; Tamb = 25 C.
Fig.14 Typical gain reduction as a function of AGC
voltage.
120
handbook, halfpage
Vunw
(dBμV)
110
MLE243
handbook,1h6alfpage
ID
(mA)
12
MLE244
100
8
90
4
80
0
10
20
30
40
50
gain reduction (dB)
VDS = 5 V; VGG = 5 V; RG1 = 150 k (connected to VGG);
see Fig.21; f= 50 MHz; funw = 60 MHz; Tamb = 25 C.
Fig.15 Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical
values.
0
0
10
20
30
40
50
gain reduction (dB)
VDS = 5 V; VGG = 5 V; RG1 = 150 k (connected to VGG);
see Fig.21; f= 50 MHz; Tamb = 25 C.
Fig.16 Drain current as a function of gain
reduction; typical values.
2003 Nov 14
8
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