BD6373GW Ver la hoja de datos (PDF) - ROHM Semiconductor
Número de pieza
componentes Descripción
Fabricante
BD6373GW
ROHM Semiconductor
BD6373GW Datasheet PDF : 18 Pages
| |||
BD6373GW, BD6873KN, BD6753KV
Technical Note
6) Charge pump (BD6753KV)
Each output H-bridge of the BD6753KV on the high and low sides consists of Nch DMOS. Therefore, the gate voltage VG
should be higher than the VM voltage to drive the Nch DMOS on the high side.The BD6753KV has a built-in charge
pump circuit that generates VG voltage by connecting an external capacitor (0.01μF to 0.1μF).
If a 0.1μF capacitor is connected between: CP1 and CP2, CP3 and CP4, VG and GND
Then, VG pin output voltage will be:
VM1 + (VCC 2)
If a 0.1μF capacitor is connected between:
CP1 and CP2, VG and GND
CP4 and VG pins are shorted, and CP3 pin is open
Then, VG pin output voltage will be:
VM1 + VCC
The VM1 to VM4 respectively can be set to voltages different to one another. In order to ensure better performance, the
voltage differential between VG and VM must be 4.5V or higher, and the VG voltage must not exceed the absolute
maximum rating of 18V.
7) Serial interface (BD6753KV)
The BD6753KV provides an 8-bit, 3-line serial interface for setting output modes. DATA is sent to the internal shift register
during the STROBE low interval at the CLK rising edge. Shift register data is written to the IC's internal 6-bit memory at
the STROBE rising edge, according to the addresses stored in Bit[7] and Bit[6]. The serial data input order is Bit[0] to
Bit[7]. Serial settings are reset when the PS pin changes to Low-level control voltage, triggering standby mode. Serial
settings are also reset when the UVLO circuit operates.
BD6753KV Serial Resistor Bit Map
No.
ADDRESS BIT
Bit[7]
Bit[6]
Bit[5]
Bit[4]
DATA BIT
Bit[3]
Bit[2]
Bit[1]
Bit[0]
00H
0
0
mod2
mod1
p2a
p2b
p1a
p1b
01H
0
1
mod4
mod3
p4a
p4b
p3a
p3b
02H
1
0
mod6
mod5
p6a
p6b
p5a
p5b
STROBE
CLK
Timing of input serial data
writing to internal register
Timing of register data writing to
internal memory
100%
0%
100%
DATA
Bit[0] Bit[1] Bit[2] Bit[3] Bit[4] Bit[5] Bit[6] Bit[7]
Bit[0] Bit[1] Bit[5] Bit[6] Bit[7]
0%
100%
DATA BITS
ADDRESS BITS
0%
DATA BITS
ADDRESS BITS
Fig.22 BD6753KV Sequence of Serial Control Input
●I/O Truth Table
BD6373GW Full-ON Driver ch1 to ch2 I/O Truth Table
Drive mode
INPUT
ENABLE12 INPUTx
OUTPUT
OUTxA OUTxB
H
X
Z
Z
EN/IN
L
L
H
L
L
H
L
H
Output mode
Standby
CW
CCW
BD6373GW Full-ON Driver ch3 to ch4 I/O Truth Table
Drive mode
INPUT
ENABLE34 INPUTx
OUTPUT
OUTxA OUTxB
H
X
Z
Z
EN/IN
L
L
H
L
L
H
L
H
Output mode
Standby
CW
CCW
BD6373GW Full-ON Driver ch5 to ch6 I/O Truth Table
Drive mode
INPUT
INPUTx BRAKEx
OUTPUT
OUTxA OUTxB
Output mode
L
L
H
L
CW
IN/IN
H
L
L
H
CCW
X
H
L
L
Brake
L: Low, H: High, X: Don't care, Z: High impedance
At CW, current flows from OUTA to OUTB. At CCW, current flows from OUTB to OUTA.
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
12/17
2009.06 - Rev.A
Share Link: