BCM1255 Ver la hoja de datos (PDF) - Broadcom Corporation
Número de pieza
componentes Descripción
Fabricante
BCM1255 Datasheet PDF : 2 Pages
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OVERVIEW
Debug/ Bus
Trace
SB -1
Core
SB-1
Core
512K
L2 Cache
Serial
Interfaces
Dual
SMBus
I/O
Bridge
64-Bit
PCI -X
256 Bits
ZBbus TM
½ core clock; 128 Gbps @ 1 GHz
DMA
DMA
DMA
DMA
10/100/
1000
MAC
10/100/
1000
MAC
10/100/
1000
MAC
10/100/
1000
MAC
FIFO
DDR
Memory
Controller
Data
Mover
GPIO/
Interrupt/
PCMCIA
Generic Bus
&
Flash I/O
100 Gbps
8 Gbps
4x GMII
8b/16b FIFO
1 Gbps
The BCM1255 device is an MIPS64 processor core-based system-on-a-
chip (SOC) that offers industry-leading performance, high functional
integration, and low-power levels required by next-generation
computing, storage, and networking applications.
The BCM1255 is a chip multiprocessor (CMP) system consisting of two
Broadcom SB-1 high-performance MIPS64 CPUs, a shared 512-KB L2
cache, a DDR memory controller, and integrated I/O. All major blocks
of the processor are connected together via the ZBbus, a high-speed,
split-transaction multiprocessor bus. The bus implements the standard
MESI protocol to ensure coherency between the two CPUs, L2 cache,
I/O agents, and memory. Four Gigabit-Ethernet MACs (10/100/1000)
enable easy interfacing to LANs or control backplanes. To enable higher
data rates (or in cases where Ethernet protocol processing is not
required), the Gigabit-Ethernet MACs can be configured as 8-bit and/or
16-bit packet FIFOs. The BCM1255 also integrates a 64-bit, 133-MHz
PCI-X local bus for direct connection to I/O devices. Four serial ports are
available for use as UARTs for console ports.
To enable low-chip count systems, the BCM1255 also includes a
configurable generic bus that allows glueless connection of a boot ROM
or flash memory and simple I/O peripherals. On-chip debug, trace, and
performance monitoring functions assist both hardware and software
designers in debugging and tuning the system. The system can be run in
either big-endian or little-endian mode.
Implementation of MIPS64 ISA
The SB-1 CPU core is a high-performance implementation of the
standard MIPS64 ISA that incorporates the MIPS-3D and MIPS-MDMX
application-specific extensions (ASEs). The core supports a 4-issue
enhanced skew pipeline and can dispatch up to two memory and two
ALU (integer, floating point, MDMX, or MIPS-3D) instructions per
cycle.
Next Generation Broadband Processors
BCM1255 BCM1280 BCM1455 BCM1480
# of CPUs 2
2
4
4
L2 Cache 512 KB 1 MB 1 MB 1 MB
DDR2 Support Yes
Yes
Yes
Yes
# of MACs 4 GMII 4 GMII 4 GMII 4 GMII
PCI-X 1 x 64-bit 1 x 64-bit 1 x 64-bit 1 x 64-bit
# of SPI-4/HT Ports 0
3
0
3
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or its subsidiaries in the United States and certain other countries. All other trademarks mentioned are the
property of their respective owners.
®
BROADCOM CORPORATION
16215 Alton Parkway, P.O. Box 57013
Irvine, California 92619-7013
© 2004 by BROADCOM CORPORATION. All rights reserved.
1255-PB01-R
09/30/04
Phone: 949-450-8700
Fax: 949-450-8710
E-mail: info@broadcom.com
Web: www.broadcom.com
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