SP3486EP Ver la hoja de datos (PDF) - Signal Processing Technologies
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SP3486EP Datasheet PDF : 9 Pages
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PINOUT — SP3486
DI1 1
1
DO1A 2
DO1B 3
EN 4
DO2B 5
DO2A 6
2
DI2 7
GND 8
SP3486 16 VCC
15 DI4
4
14 DO4A
13 DO4B
12 EN
11 DO3B
10 DO3A
3
9 DI3
SP3486 PINOUT
Pin 1 — DI1 — Driver 1 Input — If Driver 1 output
is enabled, logic 0 on DI1 forces driver output
DO1A low and DO1B high. A logic 1 on DI1 with
Driver 1 output enabled forces driver DO1A high
and DO1B low.
Pin 2 — DO1A — Driver 1 output A.
Pin 3 — DO1B — Driver 1 output B.
Pin 4 — EN — Driver Output Enable. Please refer
to SP3486 Truth Table (1).
Pin 5 — DO2B — Driver 2 output B.
Pin 6 — DO2A — Driver 2 output A.
Pin 7 — DI2 — Driver 2 Input — If Driver 2 output
is enabled, logic 0 on DI2 forces driver output
DO2A low and DO2B high. A logic 1 on DI2 with
Driver 2 output enabled forces driver DO2A high
and DO2B low.
D
VCC
R
VOD
R
VOC
GENERATOR
(NOTE 1)
VDM
S1
D
50Ω
VCC
RL = 27Ω
OUT
CL = 15PF
(NOTE 2)
VOM =
VOH + VOL
2
1.5V
Figure 2. Driver Propagation Delay Test Circuit
Pin 8 — GND — Digital Ground.
Pin 9 — DI — Driver 3 Input — If Driver 3 output
3
is enabled, logic 0 on DI forces driver output
3
DO A low and DO B high. A logic 1 on DI with
3
3
3
Driver 3 output enabled forces driver DO3A high
and DO B low.
3
Pin 10 — DO3A — Driver 3 output A.
Pin 11 — DO3B — Driver 3 output B.
Pin 12 — EN — Driver Output Disable. Please
refer to SP486 Truth Table (1).
GENERATOR
(NOTE 1)
S1
D
CL = 50pF
(NOTE 2)
50Ω
OUT
RL = 110Ω
VOM =
VOH + VOL
2
1.5V
Figure 3. Driver Enable and Disable Timing Circuit,
Output HIGH
S1
0V OR 3V
D
VCC
RL = 110Ω
OUT
GENERATOR
(NOTE 1)
CL = 50pF
(NOTE 2)
50Ω
Figure 1. Driver DC Test Load Circuit
Figure 4. Driver Enable and Disable Timing Circuit,
Output LOW
10/15/02
SP3486/3487 Low Power Quad RS485/422 Line Drivers
3
© Copyright 2002 Sipex Corporation
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