HSP48901JC-30 Ver la hoja de datos (PDF) - Intersil

Número de pieza

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Fabricante

HSP48901JC-30

3 x 3 Image Filter

Intersil 

Pin Descriptions

NAME

PLCC PIN

VCC

9, 27, 45, 61

GND

CLK

DIN1(7-0)

18, 29, 38, 56

28

1-8

DIN2(7-0)

DIN3(7-0)

CIN7-0

10-17

19-26

30-37

DOUT19-0

FRAME

46-55, 57-60,

62-67

44

HOLD

40

A2-0

LD

41-43

39

HSP48901

TYPE

I

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DESCRIPTION

The +5V power supply pins. 0.1µF capacitors between the VCC and GND pins are

recommended.

The device ground.

Input and System clock. Operations are synchronous with the rising edge of this clock signal.

Pixel Data Input Bus #1. These inputs are used to provide 8-bit pixel data to the HSP48901.

The data must be provided in a synchronous fashion, and is latched on the rising edge of the

CLK signal. The DIN1(0-7) inputs are also used to input data when operating in the 9-Tap

FIR mode.

Pixel Data Input Bus #2. Same as above. These inputs should be grounded when operating

in the 1D mode.

Pixel Data Input Bus #3. Same as above. These inputs should be grounded when operating

in the 1D mode.

Coefficient Data Input Bus. This input bus is used to load the Coefficient Mask Register(s)

and the Initialization Register. The register to be loaded is defined by the register address

bits A0-2. The CIN0-7 data is loaded to the addressed register through the use of the LD

input.

Output Data Bus. This 20-Bit output port is used to provide the convolution result. The result

is the sum of products of the input data samples and their corresponding coefficients.

FRAME is an asynchronous new frame or vertical sync input. A low on this input resets all

internal circuitry except for the Coefficient and INT Registers. Thus, after a FRAME reset has

occurred, a new frame of pixels may be convolved without reloading these registers.

The Hold Input is used to gate the clock from all of the internal circuitry of the HSP48901.

This signal is synchronous, is sampled on the rising edge of CLK and takes effect on the

following cycle. While this signal is active (high), the clock will have no effect on the

HSP48901 and internal data will remain undisturbed.

Control Register Address. These lines are decoded to determine which register in the control

logic is the destination for the data on the CIN0-7 inputs. Register loading is controlled by

the A0-2 and LD inputs.

Load Strobe. LD is used for loading the Internal Registers of the HSP48901. The rising edge

of LD will latch the CIN0-7 data into the register specified by A0-2. The Address on A0-2

must be setup with respect to the falling edge of LD and must be held with respect to the

rising edge of LD.

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