AY0438 Ver la hoja de datos (PDF) - Microchip Technology
Número de pieza
componentes Descripción
Fabricante
AY0438 Datasheet PDF : 11 Pages
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AY0438
FIGURE 1: PIN DESCRIPTIONS
Pin # (PDIP Only)
1
2
3-29, 32, 33, 37-39
30
31
34
35
36
40
Name
VDD
Load
Seg 1-32
BP
LCDΦ
Data In
Data Out
VSS
Clock
Direction
-
Input
Output
Output
Input
Input
Output
Ground
Input
Description
Supply voltage
Latch data from registers
Direct drive outputs
Backplane drive output
Backplane drive input
Data input to shift register
Data output from shift register
Ground
System clock input
FIGURE 2: BLOCK DIAGRAM
Data in
Clock
32-bit Static Shift Register
Load
32 Latches
Data out
FIGURE 3: BACKPLANE AND SEGMENT
OUTPUT
SEG On
32 Segment Drivers
LCDΦ
LCD AC
Generator
32 Outputs
Backplane
output
Backplane
SEG Off
FIGURE 4: TIMING DIAGRAM
CLOCK
Data in
Data out
Load
START
1
SEG 32
1/f
31
SEG 2
32
SEG 1
tDS
tDH
tPD
tPW
1.0 OPERATION:
1.1 Data In and Clock
The shift register shifts and outputs on the falling edge
of the clock. Every clock falling edge does a logical left
shift. As an example, if 32 clock pulses are supplied as
in Figure 4, then the data input at the first clock will out-
put at SEG 32, and the last data input (# 32) will output
at SEG 1 when a LOAD signal is enabled (Figure 2). It
is recommended that a complete 32 bit transfer be
done every time the outputs are updated. A logic 1 at
the Data In causes the corresponding segment to be
DS70010I-page 2
enabled or visible, i.e. the output at Segment Output is
180° out-of-phase with the Backplane output
(Figure 3).
1.2 Load
A logic 1 at the Load input (Figure 2) causes the paral-
lel load of the data in the shift register into the latches
that control the segment drivers. If the Load signal is
tied high, then the latches become transparent and the
segment drivers are always connected to the shift reg-
isters.
© 1995 Microchip Technology Inc.
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