AWC6340 Ver la hoja de datos (PDF) - ANADIGICS
Número de pieza
componentes Descripción
Fabricante
AWC6340 Datasheet PDF : 10 Pages
| |||
AWC6340
APPLICATION INFORMATION
To ensure proper performance, refer to all related
Application Notes on the ANADIGICS web site:
http://www.anadigics.com
Shutdown Mode
The power amplifier may be placed in a shutdown
mode by applying logic low levels (see Operating
Ranges table) to the VEN and VMODE voltages.
The Bias Control table below lists the recommended
modes of operation for various applications.
Two operating modes are recommended to optimize
current consumption. High Bias/High Power operating
mode is for POUT levels > 15 dBm. At about 15 dBm,
the PA should be “Mode Switched” to Low Power Mode.
Bias Modes
The power amplifier may be placed in either Low or
High Bias modes by applying the appropriate logic
level (see Operating Ranges table) to the VMODE pin.
Vcontrols
Venable/Vmode(s)
On Sequence Start
T_0 N =0 µ
ON Sequence
Rise/Fall Max 1µS
Defined at 10% to 90%
of Min/Max Voltage
Off Sequence Start
T_0FF= 0µ
OFF Sequence
RFIN
notes 1,2
VEN
VCC
note 1
T_0N+1µS
T_0N+3 µS
T_0FF+2µS T_0FF+3µS
Referenced After 90% of Rise
Time
Referenced Before10% of Fall
Time
Figure 3: Recommended ON/OFF Timing Sequence
Notes:
(1) Level might be changed after RF is ON.
(2) RF OFF defined as PIN ≤ -30 dBm.
(3) Switching simultaneously between VMODE and VEN is not recommended.
Table 5: Bias Control
APPLICATION
Low power
High power
Shutdown
POUT
LEVELS
BIAS
MODE
VEN
VMODE
≤ +15 dBm
Low
+1.8 V +1.8 V
> +15 dBm High +1.8 V 0 V
-
Shutdown 0 V
0V
VCC
3.1 - 4.35 V
3.1 - 4.35 V
3.1 - 4.35 V
VBATT
> 3.1 V
> 3.1 V
> 3.1 V
5
PRELIMINARY DATA SHEET - Rev 1.8
02/2012
Share Link: 