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ATTINY48(2008) Ver la hoja de datos (PDF) - Atmel Corporation

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ATTINY48 Datasheet PDF : 22 Pages
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ATtiny48/88
2. Overview
The ATtiny48/88 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATtiny48/88 achieves
throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con-
sumption versus processing speed.
2.1 Block Diagram
Figure 2-1. Block Diagram
Watchdog
Timer
Watchdog
Oscillator
Oscillator
Circuits /
Clock
Generation
EEPROM
Power
Supervision
POR / BOD &
RESET
Flash
debugWIRE
Program
Logic
SRAM
CPU
8008BS–AVR–06/08
8bit T/C 0
16bit T/C 1
Analog
SPI
Comp.
A/D Conv.
2
6
Internal
Bandgap
TWI
PORT D (8)
PORT B (8)
PORT C (8)
PORT A (4)
PD[0..7]
PB[0..7]
RESET
CLKI
PC[0..7] PA[0..3] (in TQFP and MLF)
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
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