ATV2500L-35JC Ver la hoja de datos (PDF) - Atmel Corporation
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ATV2500L-35JC Datasheet PDF : 15 Pages
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ATV2500H/L
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATV2500H/L fuse patterns. Once programmed, the
outputs will read programmed during verify. The security
fuse should be programmed last, as its effect is immediate.
The security fuse also inhibits preload and Q2 observabil-
ity.
Atmel CMOS PLDs
Atmel's Erasable Programmable Logic Devices utilize an
advanced 1.25-micron CMOS EPROM technology. This
technology's state of the art features are the optimum com-
bination for PLDs:
• CMOS technology provides high speed, low power, and
high noise immunity.
• EPROM technology is the most cost effective method for
producing PLDs - surpassing bipolar fusible link
technology in low cost, while providing the necessary
reprogrammability.
• EPROM reprogrammability, which is 100% tested before
shipment, provides inherently better programmability and
reliability than one-time fusible PLDs.
• Atmel's EPROM process has proven extremely reliable
in the volume production of a full line of advanced
EPROM memory products, from 64K to one-megabit
devices.
Using the ATV2500H/L's Many
Advanced Features
The ATV2500H/L's flexibility puts more usable gates in 40
pins than other PLDs. Some of the ATV2500H/L's key fea-
tures are:
• Asynchronous Clocks -
Each of the flip-flops in the ATV2500H/L has a dedicated
product term driving the clock. The user is no longer con-
strained to using one clock for all the registers. Buried state
machines, counters, and registers can all coexist in one
device, while running on separate clocks. The ATV2500H/L
clock period matches that of similar synchronous devices.
• A Total of 48 Registers -
The ATV2500H/L provides two flip-flops for each output
macrocell - a total of 48. Each register has its own clock
and reset product terms, as well as its own sum term.
• Independent I/O Pin and Feedback Paths -
Each I/O pin on the ATV2500/H has a dedicated input path.
Each of the 48 registers has individual feedback terms into
the array. This feature, combined with individual product
terms for each I/O's output enable, facilitates designs using
bi-directional I/O buses.
• Three Sum Terms per Macrocell -
The ATV2500H/L macrocell can be configured with one
SUM term feeding the output, and still have two SUM terms
feeding the flip-flops. This is the simplest method for inter-
facing with an I/O bus, and no flip-flops need be sacrificed.
• Combinable Sum Terms -
Each output macrocell's three SUM terms can be combined
in an OR gate before the output or the register. This pro-
vides up to twelve product terms per output or flip-flop.
When the registered output configuration is chosen, eight
terms are automatically available to D1. The four terms
feeding D2 can also be shared with D1, giving it a total of
twelve. In the combinatorial mode, four, eight, or twelve
terms can feed the output, with the middle four still driving
D1 and the bottom four still driving D2.
Programming Software Support
Software which is capable of transforming Boolean equa-
tions, state machine descriptions and truth tables into
JEDEC files for the ATV2500H/L is currently available from
several PLD software vendors. Please refer to the Pro-
grammable Logic Development Tools section for a com-
plete listing of the PLD software support.
Erasure Characteristics
The entire memory array of an ATV2500H/L is erased after
exposure to ultraviolet light at a wavelength of 2537 Å.
Complete erasure is assured after a minimum of twenty
minutes exposure using 12,000 µW/cm2 intensity lamps
spaced one inch away from the chip. Minimum erase time
for lamps at other intensity ratings can be calculated from
the minimum integrated erasure dose of fifteen W•sec/cm2.
To prevent unintentional erasure, an opaque label is rec-
ommended to cover the clear window on any UV erasable
PLD which will be subjected to continuous fluorescent
indoor lighting or sunlight.
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