ATTINY13A Ver la hoja de datos (PDF) - Atmel Corporation
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componentes Descripción
Fabricante
ATTINY13A Datasheet PDF : 20 Pages
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5. Instruction Set Summary
Mnemonics
ADD
ADC
ADIW
SUB
SUBI
SBC
SBCI
SBIW
AND
ANDI
OR
ORI
EOR
COM
NEG
SBR
CBR
INC
DEC
TST
CLR
SER
RJMP
IJMP
RCALL
ICALL
RET
RETI
CPSE
CP
CPC
CPI
SBRC
SBRS
SBIC
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
BRID
SBI
CBI
LSL
LSR
ROL
Operands
Description
ARITHMETIC AND LOGIC INSTRUCTIONS
Rd, Rr
Add two Registers
Rd, Rr
Add with Carry two Registers
Rdl,K
Add Immediate to Word
Rd, Rr
Subtract two Registers
Rd, K
Subtract Constant from Register
Rd, Rr
Subtract with Carry two Registers
Rd, K
Subtract with Carry Constant from Reg.
Rdl,K
Subtract Immediate from Word
Rd, Rr
Logical AND Registers
Rd, K
Logical AND Register and Constant
Rd, Rr
Logical OR Registers
Rd, K
Logical OR Register and Constant
Rd, Rr
Exclusive OR Registers
Rd
One’s Complement
Rd
Two’s Complement
Rd,K
Set Bit(s) in Register
Rd,K
Clear Bit(s) in Register
Rd
Increment
Rd
Decrement
Rd
Test for Zero or Minus
Rd
Clear Register
Rd
Set Register
BRANCH INSTRUCTIONS
k
Relative Jump
Indirect Jump to (Z)
k
Relative Subroutine Call
Indirect Call to (Z)
Subroutine Return
Interrupt Return
Rd,Rr
Compare, Skip if Equal
Rd,Rr
Compare
Rd,Rr
Compare with Carry
Rd,K
Compare Register with Immediate
Rr, b
Skip if Bit in Register Cleared
Rr, b
Skip if Bit in Register is Set
P, b
Skip if Bit in I/O Register Cleared
P, b
Skip if Bit in I/O Register is Set
s, k
Branch if Status Flag Set
s, k
Branch if Status Flag Cleared
k
Branch if Equal
k
Branch if Not Equal
k
Branch if Carry Set
k
Branch if Carry Cleared
k
Branch if Same or Higher
k
Branch if Lower
k
Branch if Minus
k
Branch if Plus
k
Branch if Greater or Equal, Signed
k
Branch if Less Than Zero, Signed
k
Branch if Half Carry Flag Set
k
Branch if Half Carry Flag Cleared
k
Branch if T Flag Set
k
Branch if T Flag Cleared
k
Branch if Overflow Flag is Set
k
Branch if Overflow Flag is Cleared
k
Branch if Interrupt Enabled
k
Branch if Interrupt Disabled
BIT AND BIT-TEST INSTRUCTIONS
P,b
Set Bit in I/O Register
P,b
Clear Bit in I/O Register
Rd
Logical Shift Left
Rd
Logical Shift Right
Rd
Rotate Left Through Carry
8126ES–AVR–07/10
ATtiny13A
Operation
Rd ← Rd + Rr
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
Rd ← Rd • K
Rd ← Rd v Rr
Rd ← Rd v K
Rd ← Rd ⊕ Rr
Rd ← 0xFF − Rd
Rd ← 0x00 − Rd
Rd ← Rd v K
Rd ← Rd • (0xFF - K)
Rd ← Rd + 1
Rd ← Rd − 1
Rd ← Rd • Rd
Rd ← Rd ⊕ Rd
Rd ← 0xFF
PC ← PC + k + 1
PC ← Z
PC ← PC + k + 1
PC ← Z
PC ← STACK
PC ← STACK
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
Rd − Rr − C
Rd − K
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
I/O(P,b) ← 1
I/O(P,b) ← 0
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Flags
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
None
None
None
None
None
I
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Z,C,N,V
Z,C,N,V
Z,C,N,V
#Clocks
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
3
3
4
4
1/2/3
1
1
1
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
2
2
1
1
1
9
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